參數(shù)資料
型號： PSD4235G2V-C-12UI
廠商： 意法半導體
英文描述： Flash In-System-Programmable Peripherals for 16-Bit MCUs
中文描述： Flash在系統(tǒng)可編程外設的16位微控制器
文件頁數(shù)： 5/93頁
文件大?。?/td> 503K
代理商： PSD4235G2V-C-12UI
PSD4000 Series
Preliminary Information
10
Pin*
(TQFP
Pin Name Pkg.)
Type
Description
PE1
72
I/O
Port E, PE1. This port is pin configurable and has multiple
CMOS
functions:
or Open
1. MCU I/O — standard output or input port.
Drain
2. Latched address output.
3. TCK input for JTAG/ISP interface (Schmidt Trigger).
PE2
73
I/O
Port E, PE2. This port is pin configurable and has multiple
CMOS
functions:
or Open
1. MCU I/O — standard output or input port.
Drain
2. Latched address output.
3. TDI input for JTAG/ISP interface.
PE3
74
I/O
Port E, PE3. This port is pin configurable and has multiple
CMOS
functions:
or Open
1. MCU I/O — standard output or input port.
Drain
2. Latched address output.
3. TDO output for JTAG/ISP interface.
PE4
75
I/O
Port E, PE4. This port is pin configurable and has multiple
CMOS
functions:
or Open
1. MCU I/O — standard output or input port.
Drain
2. Latched address output.
3. TSTAT output for the ISP interface.
4. Rdy/Bsy — for in-circuit Parallel Programming.
PE5
76
I/O
Port E, PE5. This port is pin configurable and has multiple
CMOS
functions:
or Open
1. MCU I/O — standard output or input port.
Drain
2. Latched address output.
3. TERR active low output for ISP interface.
PE6
77
I/O
Port E, PE6. This port is pin configurable and has multiple
CMOS
functions:
or Open
1. MCU I/O — standard output or input port.
Drain
2. Latched address output.
3. Vstby — SRAM standby voltage input for battery
backup SRAM
PE7
78
I/O
Port E, PE7. This port is pin configurable and has multiple
CMOS
functions:
or Open
1. MCU I/O — standard output or input port.
Drain
2. Latched address output.
3. Vbaton — battery backup indicator output. Goes high when
power is drawn from an external battery.
PF0-PF7
31-38
I/O
Port F, PF0-7. This port is pin configurable and has multiple
CMOS
functions:
or Open
1. MCU I/O — standard output or input port.
Drain
2. Input to the PLD.
3. Latched address outputs.
4. As address A1-3 inputs in 80C51XA mode (PF0 is grounded)
5. As data bus port (D0-7) in non-multiplexed bus configuration
6. MCU reset mode.
PG0-PG7 21-28
I/O
Port G, PG0-7. This port is pin configurable and has multiple
CMOS
functions:
or Open
1. MCU I/O — standard output or input port.
Drain
2. Latched address outputs.
3. As data bus port (D8-15) in non-multiplexed bus configuration.
4. MCU reset mode.
GND
8,30,
49,50,
70
VCC
9,29,
69
Table 5.
PSD4000
Pin
Descriptions
(cont.)
相關PDF資料
PDF描述
PSD4235G2V-C-15B81 Flash In-System-Programmable Peripherals for 16-Bit MCUs
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