參數(shù)資料
型號: PPC405EX-SpAfffTx
廠商: Applied Micro Circuits Corp.
英文描述: PowerPC 405EX Embedded Processor
中文描述: 嵌入式處理器的PowerPC 405EX
文件頁數(shù): 37/67頁
文件大?。?/td> 457K
代理商: PPC405EX-SPAFFFTX
PPC405EX – PowerPC 405EX Embedded Processor
Revision 1.09 - August 21, 2007
AMCC Proprietary
37
Preliminary Data Sheet
Pin Group List
The following table provides a summary of the number of package pins (balls) associated with each functional
interface group.
In the table “Signal Functional Description” on page 38, each external signal is listed along with a short description
of the signal function. Active-low signals (for example, Halt) are marked with an overline. See the preceding table,
“Signals Listed Alphabetically” on page 17, for the pin (ball) number to which each signal is assigned.
Shared Pins
Some signals are shared on the same package pin so that the pin can be used for different functions. In most
cases, the signal names shown in this table are not accompanied by signal names that might share the same pin.
If you need to know what, if any, signals are shared with a particular signal, look up the name in “Signals Listed
Alphabetically” on page 17. It is expected that in any single application a particular pin will always be programmed
to serve the same function. The flexibility of sharing allows a single chip to offer a richer pin selection than would
otherwise be possible.
Initialization Strapping
One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only
during reset and are used for other functions during normal operation (see “Initialization” on page 65). Note that the
use of these pins for strapping is not considered multiplexing since the strapping function is not programmable.
Pull-Up and Pull-Down Resistors
Pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in an
appropriate state. The recommended pull-up value of 3k
Ω
to +3.3V and pull-down value of 1k
Ω
to GND, applies
only to individually terminated signals. To prevent possible damage to the device, I/Os capable of becoming
outputs
must never
be tied together and terminated through a common resistor.
If your system-level test methodology permits, input-only signals can be connected together and terminated
through either a common resistor or directly to +3.3V or GND. When a resistor is used, its value must ensure that
the grouped I/Os reach a valid logical zero or logical one state when accounting for the total input current into the
PPC405EX.
Table 5. Pin Groups
Group
No. of Pins
246
Total Signal Pins
V
DD
OV
DD
EOV
DD
SV
DD
GND
AV
DD
AHV
DD
SAV
DD
SAGND
17
20
6
10
71
7
2
1
1
EAV
DD
EAGND
1
1
AGND
4
Total Power Pins
Reserved
Total Pins
141
1
388
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