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參數(shù)資料
| 型號： | PT7D5820 |
| 英文描述： | 100V Single N-Channel HEXFET Power MOSFET in a D2Pak package |
| 中文描述： | 大型數(shù)字開關(guān)？ |
| 文件頁數(shù)： | 11/39頁 |
| 文件大?。?/td> | 530K |
| 代理商： | PT7D5820 |
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Data Sheet
PT7D5820/5820L Large Digital Switch
11
PT0098(12/03)
Ver:1
The connection memory data can be accessed via the micro-
processor interface through the D0 to D15 pins. The address-
ing of the device internal registers, data and connection memo-
ries is performed through the address input pins and the Memory
Select (MS) bit of the control register. For details on device
addressing, see Control Register bits description.
Serial Data Interface Timing
The master clock frequency must always be twice the data rate,
the master clock (CLK) must be either at 4.096, 8.192 or 16.384
MHz for serial data rate of 2.048, 4.096 or 8.192 Mb/s respec-
tively, the input and output stream data rates will always be
identical.
The PT7D5820/5820L provides two different serial interface tim-
ing modes controlled by the WFPS pin. If the WFPS pin is low,
the PT7D5820/5820L is in ST-BUS/GCI mode. If the WFPS pin is
high, the PT7D5820/5820L is in the WFP frame alignment mode.
In ST-BUS/GCI mode, the input 8 kHz frame pulse can be in
either ST-BUS or GCI format. The PT7D5820/5820L automati-
cally detects the presence of an input frame pulse and identifies
it as either ST-BUS or GCI. In ST-BUS format, every second
falling edge of the master clock marks a bit boundary and the
data is clocked in on the rising edge of CLK, three quarters of
the way into the bit cell, see in
Figure 13
. In GCI format, every
second rising edge of the master clock marks the bit boundary
and data is clocked in on the falling edge of CLK at three quar-
ters of the way into the bit cell, see
Figure 14
.
Wide Frame Pulse (WFP) Frame Alignment Timing
When the device is in WFP frame alignment mode, the CLK
input must be at 16.384 MHz, the FE/HCLK input is 4.096
MHz and the 8 kHz frame pulse is in ST-BUS format. The
timing relationship between CLK, HCLK and the frame pulse
is defined in
Figure 15
.
When WFPS pin is high, the frame alignment evaluation fea-
ture is disabled, but the frame input offset registers may still be
programmed to compensate for the varying frame delays on
the serial input streams.
Switching Configurations
The PT7D5820/5820L maximum non-blocking switching con-
figurations is determined by the data rates selected for the se-
rial inputs and outputs. The switching configuration is selected
by two DR bits in the IMS register.
Table 1. Switching Configuration
Serial Interface
Data Rate
Master Clock
Required (MHz)
Matrix Channel
Capacity
2.048 Mb/s
4.096
512 x 512
4.096 Mb/s
8.192
1024 x 1024
8.192 Mb/s
16.384
2048 x 2048
Input Frame Offset Selection
Input frame offset selection allows the channel alignment of
individual input streams to be offset with respect to the output
stream channel alignment (i.e. F0i). This feature is useful in
compensating for variable path delays caused by serial
backplanes of variable lengths, which may be implemented in
large centralized and distributed switching systems.
Each input stream can have its own delay offset value by pro-
gramming the frame input offset (FOR) registers. Possible ad-
justment can range up to + 2 bit cell width forward with resolu-
tion of 1/4 bit cell width. The output frame offset cannot be
offset or adjusted. See
Figure 9
&
Table 9
for delay offset
programming.
Serial Input Frame Alignment Evaluation
The PT7D5820/5820L provides the frame evaluation (FE) input
to determine different data input delays with respect to the
frame pulse F0i.
A measurement cycle is started by setting the start frame evalu-
ation (SFE) bit low for at least one frame. Then the evaluation
starts when the SFE bit in the IMS register is changed from low
to high. Two frames later, the complete frame evaluation (CFE)
bit of the frame alignment register (FAR) changes from low to
high to signal that a valid offset measurement is ready to be
read from bits 0 to 11 of the FAR register. The SFE bit must be
set to zero before a new measurement cycle started.
In ST-BUS mode, the falling edge of the frame measurement
signal (FE) is evaluated against the falling edge of the ST-BUS
frame pulse. In GCI mode, the rising edge of FE is evaluated
against the rising edge of the GCI frame pulse. See
Figure 8
for
the description of the frame alignment register.
Table 1 summarizes the switching configurations and the rela-
tionship between different serial data rates and the master clock
frequencies.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PT7FFSDGY | 制造商:Hubbell Wiring Device-Kellems 功能描述:FLUSH FRPT, 1 SERV, FURN FEED, GY |
| PT7FFSDI | 制造商:Hubbell Wiring Device-Kellems 功能描述:FLUSH FRPT, 1 SERV, FURN FEED, IV |
| PT7FSD | 制造商:Hubbell Wiring Device-Kellems 功能描述:THRU-FLOOR FITTING, 3 FLUSH FRPT |
| PT7FSDBLA | 制造商:Hubbell Wiring Device-Kellems 功能描述:FLUSH FRPT, W/20A DUP/TELE/DATA,BK |
| PT7FSDBRA | 制造商:Hubbell Wiring Device-Kellems 功能描述:FLUSH FRPT, W/20A DUP/TELE/DATA,BR |
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