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參數(shù)資料
| 型號(hào)： | PT7D5820 |
| 英文描述： | 100V Single N-Channel HEXFET Power MOSFET in a D2Pak package |
| 中文描述： | 大型數(shù)字開關(guān)？ |
| 文件頁數(shù)： | 15/39頁 |
| 文件大?。?/td> | 530K |
| 代理商： | PT7D5820 |
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Data Sheet
PT7D5820/5820L Large Digital Switch
15
PT0098(12/03)
Ver:1
The control register is used to control switching operations in
the PT7D5820/5820L. It selects the internal memory locations
that specify the input and output channels selected for switch-
ing.
The data in the control register consists of the memory block
programming bit (MBP), the memory select bit (MS) and the
stream address bits (STA). The memory block programming
bit allows users to program the entire connection memory
block, (see Memory Block Programming section). The memory
select bit controls the selection of the connection memory or
the data Memory. The stream address bits define an internal
memory subsection corresponding to input or output ST-BUS
streams.
The data in the IMS register consists of block programming
bits (BPD0-BPD4), block programming enable bit (BPE), out-
put stand by bit (OSB), start frame evaluation bit (SFE) and
data rate selection bits (DR0, DR1). The block programming
and the block programming enable bits allows users to pro-
gram the entire connection memory, (see Memory Block Pro-
gramming section). If the ODE pin is low, the OSB bit enables
(if high) or disables (if low) all ST-BUS output drivers. If the
ODE pin is high, the contents of the OSB bit is ignored and all
ST-BUS output drivers are enabled.
Connection Memory Control
The contents of the CSTo bit of each connection memory loca-
tion are output on the CSTo pin once every frame. If the CSTo
bit is set high, the corresponding bit on the CSTo output is
transmitted high. If the CSTo bit is low, the corresponding bit
on the CSTo output is transmitted low. The contents of the
CSTo bits of the connection memory are transmitted sequen-
tially on to the CSTo pin and are synchronous with the data
rates on the other ST-BUS streams.
If the ODE pin or the OSB bit is high, the OE bit of each connec-
tion memory location enables (if high) or disables (if low) the
output drivers for an individual ST-BUS output stream and chan-
nel. See
Table 5
for detail.
The message channel (MC) bit of the connection memory en-
ables (if high) an associated ST-BUS output channel in mes-
sage mode. If the MC bit is low, the contents of the stream
address bit (SAB) and the channel address bit (CAB) of the
connection memory defines the source information (stream
and channel) of the time-slot that will be switched to the out-
put. When message mode is enabled, only the lower half (8
least significant bits) of the connection memory is transferred
to the ST-BUS outputs.
Bit V/C (Variable/Constant Delay) of each connection memory
location allows the per-channel selection between variable
and constant throughput delay modes.
If the LPBK bit is high, the associated ST-BUS output channel
data is internally looped back to the ST-BUS input channel
(i.e., STi n channel m data comes from the STo n channel m). If
the LPBK bit is low, the loopback feature is disabled. For proper
per-channel loopback operation, the contents of the frame de-
lay offset registers must be set to zero.
CSTo Output
The CSTo bit is output one channel before the corresponding
channel on the ST-BUS. For example, in 2Mb/s mode, the
contents of the CSTo bit in position 0 (STo0, CH0) of the
connection memory is output on the first clock cycle of chan-
nel 31 through CSTo pin. The contents of the CSTo bit in
position 32 (STo1, CH0) of the connection memory is output
on the second clock cycle of channel 31 via CSTo pin. CSTo
bit is always clocked out at bit rate of clock, and every CSTo
channel contains 16 bits. See
Figure 7
.
Figure 7. the Output of the CSTo Bit
ST
0
ST
15
ST
1
ST
2
ST
3
ST
4
ST
5
ST
6
ST
7
ST
8
ST
9
ST
10
ST
11
ST
12
ST
13
ST
14
ST
15
Channel 0
Bit 7
Channel 0
Bit 6
Channel 0
Bit 5
Channel 0
Bit 4
Channel 0
Bit 3
Channel 0
Bit 2
Channel 0
Bit 1
Channel 0
Bit 0
F0i
CLK
CSTo
Data
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