參數(shù)資料
型號： Q67100-Q2157
廠商： SIEMENS AG
英文描述： 4M x 32-Bit EDO-DRAM Module
中文描述： 4米× 32位江戶記憶體模組
文件頁數(shù)： 12/53頁
文件大?。?/td> 418K
代理商： Q67100-Q2157
HYB 39S64400/800/160BT(L)
64-MBit Synchronous DRAM
Data Book
12
12.99
terminate once the burst length has been reached. In other words, unlike burst length of 2, 3 or 8,
full page burst continues until it is terminated using another command.
Similar to the page mode of conventional DRAM’s, burst read or write accesses on any column
address are possible once the RAS cycle latches the sense amplifiers. The maximum
t
RAS
or the
refresh interval time limits the number of random column accesses. A new burst access can be
done even before the previous burst ends. The interrupt operation at every clock cycle is supported.
When the previous burst is interrupted, the remaining addresses are overridden by the new address
with the full burst length. An interrupt which accompanies an operation change from a read to a write
is possible by exploiting DQM to avoid bus contention.
When two or more banks are activated sequentially, interleaved bank read or write operations are
possible. With the programmed burst length, alternate access and precharge operations on two or
more banks can realize fast serial data access modes among many different pages. Once two or
more banks are activated, column to column interleave operation can be done between different
pages.
Refresh Mode
SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the CAS
-before-RAS refresh of conventional DRAMs. All of banks must be precharged before applying any
refresh mode. An on-chip address counter increments the word and the bank addresses and no
bank information is required for both refresh modes.
The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are
held high at a clock timing. The mode restores word line after the refresh and no external precharge
Burst Length and Sequence
Burst
Length
Starting
Address
(A2 A1 A0)
Sequential Burst Addressing
(decimal)
Interleave Burst
Addressing
(decimal)
2
xx0
xx1
0, 1
1, 0
0, 1
1, 0
4
x00
x01
x10
x11
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
8
000
001
010
011
100
101
110
111
0 1 2 3 4 5 6 7
1 2 3 4 5 6 7 0
2 3 4 5 6 7 0 1
3 4 5 6 7 0 1 2
4 5 6 7 0 1 2 3
5 6 7 0 1 2 3 4
6 7 0 1 2 3 4 5
7 0 1 2 3 4 5 6
0 1 2 3 4 5 6 7
1 0 3 2 5 4 7 6
2 3 0 1 6 7 4 5
3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3
5 4 7 6 1 0 3 2
6 7 4 5 2 3 0 1
7 6 5 4 3 2 1 0
Full Page
(optional)
nnn
Cn, Cn+1, Cn+2,.....
not supported
相關PDF資料
PDF描述
Q67100-Q2176 3.3V 1M x 64-Bit EDO-DRAM Module 3.3V 1M x 72-Bit EDO-DRAM Module
Q67100-Q2177 3.3V 1M x 64-Bit EDO-DRAM Module 3.3V 1M x 72-Bit EDO-DRAM Module
Q67100-Q2178 3.3V 1M x 64-Bit EDO-DRAM Module 3.3V 1M x 72-Bit EDO-DRAM Module
Q67100-Q2179 3.3V 1M x 64-Bit EDO-DRAM Module 3.3V 1M x 72-Bit EDO-DRAM Module
Q67100-Q2180 3.3V 2M x 64-Bit EDO-DRAM Module 3.3V 2M x 72-Bit EDO-DRAM Module
相關代理商/技術參數(shù)
參數(shù)描述
Q67100-Q2176 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3V 1M x 64-Bit EDO-DRAM Module 3.3V 1M x 72-Bit EDO-DRAM Module
Q67100-Q2177 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3V 1M x 64-Bit EDO-DRAM Module 3.3V 1M x 72-Bit EDO-DRAM Module
Q67100-Q2178 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3V 1M x 64-Bit EDO-DRAM Module 3.3V 1M x 72-Bit EDO-DRAM Module
Q67100-Q2179 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3V 1M x 64-Bit EDO-DRAM Module 3.3V 1M x 72-Bit EDO-DRAM Module
Q67100-Q2180 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3V 2M x 64-Bit EDO-DRAM Module 3.3V 2M x 72-Bit EDO-DRAM Module
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