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參數(shù)資料
| 型號(hào)： | Q67120-C508 |
| 英文描述： | IC-SM-8-BIT CPU 12-MHZ |
| 中文描述： | 集成電路釤8位CPU的12兆赫 |
| 文件頁(yè)數(shù)： | 19/121頁(yè) |
| 文件大小： | 1000K |
| 代理商： | Q67120-C508 |
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Fundamental Structure
C501
Semiconductor Group
2-3
Special Function Register PSW (Address D0H)
Reset Value : 00H
B Register
The B register is used during multiply and divide and serves as both source and destination. For
other instructions it can be treated as another scratch pad register.
Stack Pointer
The stack pointer (SP) register is 8 bits wide. It is incremented before data is stored during PUSH
and CALL executions and decremented after data is popped during a POP and RET (RETI)
execution, i.e. it always points to the last valid stack byte. While the stack may reside anywhere in
the on-chip RAM, the stack pointer is initialized to 07H after a reset. This causes the stack to begin
a location = 08H above register bank zero. The SP can be read or written under software control.
Bit
Function
CY
Carry Flag
Used by arithmetic instruction.
AC
Auxiliary Carry Flag
Used by instructions which execute BCD operations.
F0
General Purpose Flag
RS1
RS0
Register Bank select control bits
These bits are used to select one of the four register banks.
RS1
RS0
Function
OV
Overflow Flag
Used by arithmetic instruction.
F1
General Purpose Flag
P
Parity Flag
Set/cleared by hardware after each instruction to indicate an odd/even
number of “one” bits in the accumulator, i.e. even parity.
CY
AC
F0
RS1
RS0
OV
F1
P
D0H
PSW
D7H
D6H
D5H
D4H
D3H
D2H
D1H
D0H
Bit No.
MSB
LSB
0
0
Bank 0 selected, data address 00H-07H
Bank 1 selected, data address 08H-0FH
Bank 2 selected, data address 10H-17H
Bank 3 selected, data address 18H-1FH
0
1
1
0
1
1
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