參數(shù)資料
型號: Q67120-C508
英文描述: IC-SM-8-BIT CPU 12-MHZ
中文描述: 集成電路釤8位CPU的12兆赫
文件頁數(shù): 79/121頁
文件大?。?/td> 1000K
代理商: Q67120-C508
Interrupt System
C501
Semiconductor Group
7-1
7
Interrupt System
The C501 provides 6 interrupt sources with two priority levels. Four interrupts can be generated by
the on-chip peripherals (timer 0, timer 1, timer 2 and serial interface), and two interrupts may be
triggered externally (P3.2/INT0 and P3.3/INT1).
This chapter shows the interrupt structure, the interrupt vectors and the interrupt related special
function registers.
Figure 7-25
gives a general overview of the interrupt sources and illustrate the
request and the control flags which are described in the next sections.
Figure 7-25
Interrupt Structure
Timer 2 Overflow
Timer 1 Overflow
MCS01783
TF0
ET0
IE.1
P1.1/
T2EX
P3.2/
INT0
EA
IE.7
High Priority
Timer 0 Overflow
TCON.5
PT0
IP.1
Low Priority
PT1
IP.3
TCON.7
ET1
IE.3
TF1
T2CON.3
TF2
EXEN2
T2CON.7
PT2
IP.5
1
EXF2
T2CON.6
TI
1
PS
IP.4
SCON.0
ES
IE.4
RI
IE.5
IE0
EX0
IE.0
TCON.1
PX0
IP.0
ET2
IT0
IT1
PX1
IP.2
TCON.3
EX1
IE.2
IE1
INT1
P3.3/
TCON.0
TCON.2
SCON.1
TCON.0
USART
_
_
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