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參數(shù)資料
| 型號： | Q67121C2168A1 |
| 英文描述： | IC-SM-16 BIT CPU |
| 中文描述： | 集成電路的Sm - 16位CPU |
| 文件頁數(shù)： | 101/121頁 |
| 文件大?。?/td> | 1000K |
| 代理商： | Q67121C2168A1 |
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Device Specifications
C501
Semiconductor Group
10-4
Notes:
1)
Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the
V
OL
of ALE
and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise
pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,
or use an address latch with a schmitt-trigger strobe input.
2)
Capacitive loading on ports 0 and 2 may cause the
V
OH
on ALE and PSEN to momentarily fall bellow the
0.9
V
CC
specification when the address lines are stabilizing.
3)
I
PD
(Power Down Mode) is measured under following conditions:
EA = Port0 =
V
CC
; RESET =
V
SS
; XTAL2 = N.C.; XTAL1 =
V
SS
; all other pins are disconnected.
4)
I
CC
(active mode) is measured with:
XTAL1 driven with
t
CLCH
,
t
CHCL
= 5 ns,
V
IL
=
V
SS
+ 0.5 V,
V
IH
=
V
CC
– 0.5 V; XTAL2 = N.C.;
EA = Port0 = RESET=
V
CC
; all other pins are disconnected.
I
CC
would be slightly higher if a crystal oscillator is
used (appr. 1 mA).
5)
I
CC
(Idle mode) is measured with all output pins disconnected and with all peripherals disabled;
XTAL1 driven with
t
CLCH
,
t
CHCL
= 5 ns,
V
IL
=
V
SS
+ 0.5 V,
V
IH
=
V
CC
– 0.5 V; XTAL2 = N.C.;
RESET = EA =
V
SS
; Port0
= V
CC
; all other pins are disconnected;
7)
I
CC max
at other frequencies is given by:
active mode:
I
CC
= 1.27 x
f
OSC
+ 5.73
idle mode:
I
CC
= 0.28 x
f
OSC
+ 1.45 (C501-L and C501-1R only)
where
f
OSC
is the oscillator frequency in MHz.
CC
values are given in mA and measured at
V
CC
= 5 V.
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