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| 型號(hào)： | Q67121C2168A1 |
| 英文描述： | IC-SM-16 BIT CPU |
| 中文描述： | 集成電路的Sm - 16位CPU |
| 文件頁(yè)數(shù)： | 87/121頁(yè) |
| 文件大小： | 1000K |
| 代理商： | Q67121C2168A1 |
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Interrupt System
C501
Semiconductor Group
7-9
Note that if an interrupt of a higher priority level goes active prior to S5P2 in the machine cycle
labeled C3 in
figure 7-26
then, in accordance with the above rules, it will be vectored to during C5
and C6 without any instruction for the lower priority routine to be executed.
Thus, the processor acknowledges an interrupt request by executing a hardware-generated LCALL
to the appropriate servicing routine. In some cases it also clears the flag that generated the
interrupt, while in other cases it does not; then this has to be done by the user’s software. The
hardware clears the external interrupt flags IE0 and IE1 only if they were transition-activated. The
hardware-generated LCALL pushes the contents of the program counter onto the stack (but it does
not save the PSW) and reloads the program counter with an address that depends on the source of
the interrupt being vectored too, as shown in the following
table 7-9
.
Execution proceeds from that location until the RETI instruction is encountered. The RETI
instruction informs the processor that the interrupt routine is no longer in progress, then pops the
two top bytes from the stack and reloads the program counter. Execution of the interrupted program
continues from the point where it was stopped. Note that the RETI instruction is very important
because it informs the processor that the program left the current interrupt priority level. A simple
RET instruction would also have returned execution to the interrupted program, but it would have
left the interrupt control system thinking an interrupt was still in progress. In this case no interrupt of
the same or lower priority level would be acknowledged.
Table 7-9
Interrupt Source and Vectors
Interrupt Source
Interrupt Vector Address
Interrupt Request Flags
External Interrupt 0
0003H
000BH
0013H
001BH
0023H
002BH
IE0
Timer 0 Overflow
TF0
External Interrupt 1
IE1
Timer 1 Overflow
TF1
Serial Channel
RI / TI
Timer 2 Overflow / Ext. Reload
TF2 / EXF2
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相關(guān)代理商/技術(shù)參數(shù) |
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