參數(shù)資料
型號(hào)： Q67121C2168A1
英文描述： IC-SM-16 BIT CPU
中文描述： 集成電路的Sm - 16位CPU
文件頁數(shù)： 91/121頁
文件大?。?/td> 1000K
代理商： Q67121C2168A1
Power Saving Modes
C501
Semiconductor Group
8-2
8.2
Idle Mode
In the idle mode the oscillator of the C501 continues to run, but the CPU is gated off from the clock
signal. However, the interrupt system, the serial port, and all timers are further provided with the
clock. The CPU status is preserved in its entirety: the stack pointer, program counter, program
status word, accumulator, and all other registers maintain their data during idle mode.
The reduction of power consumption, which can be achieved by this feature depends on the number
of peripherals running. If all timers are stopped and the serial interfaces are not running, the
maximum power reduction can be achieved. This state is also the test condition for the idle mode
I
CC
.
So, the user has to take care which peripheral should continue to run and which has to be stopped
during idle mode. Also the state of all port pins – either the pins controlled by their latches or
controlled by their secondary functions – depends on the status of the controller when entering idle
mode.
Normally, the port pins hold the logical state they had at the time when the idle mode was activated.
If some pins are programmed to serve as alternate functions they still continue to output during idle
mode if the assigned function is on. This applies to the serial interface in case it cannot finish
reception or transmission during normal operation. The control signals ALE and PSEN are hold at
logic high levels.
As in normal operation mode, the ports can be used as inputs during idle mode. Thus a capture or
reload operation can be triggered, the timers can be used to count external events, and external
interrupts will be detected.
The idle mode is a useful feature which makes it possible to "freeze" the processor's status - either
for a predefined time, or until an external event reverts the controller to normal operation, as
discussed below. The watchdog timer is the only peripheral which is automatically stopped during
idle mode.
The idle mode is entered by setting the flag bit IDLE (PCON.0).
Note:
PCON is not a bit-addressable register, so the above mentioned sequence for entering the idle
mode is obtained by byte-handling instructions,
as shown in the following example:
ORL
PCON,#00000001B
;Set bit IDLE
The instruction that sets bit IDLE is the last instruction executed before going into idle mode.
There are two ways to terminate the idle mode:
– The idle mode can be terminated by activating any enabled interrupt. This interrupt will be
serviced and normally the instruction to be executed following the RETI instruction will be the
one following the instruction that sets the bit IDLE.
– The other way to terminate the idle mode, is a hardware reset. Since the oscillator is still
running, the hardware reset must be held active only for two machine cycles for a complete
reset.
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