參數(shù)資料
型號: Q67127-C2036SAB-C161R1-L16M
英文描述: IC-SM-16 BIT CPU
中文描述: 集成電路的Sm - 16位CPU
文件頁數(shù): 60/121頁
文件大?。?/td> 1000K
代理商: Q67127-C2036SAB-C161R1-L16M
Semiconductor Group
6-26
On-Chip Peripheral Components
C501
6.2.2.2
Auto-Reload (Up or Down Counter)
Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode.
This feature is invoked by a bit named DCEN (Down Counter Enable, SFR T2MOD, 0C9H). When
DCEN is set, timer 2 can count up or down depending on the value of pin T2EX (P1.1).
Figure 6-15
shows timer 2 automatically counting up when DCEN = 0. In this mode there are two
options selectable by bit EXEN2 in SFR T2CON.
Figure 6-15
Timer 2 Auto-Reload Mode (DCEN = 0)
If EXEN2 = 0, timer 2 counts up to FFFFH and then sets the TF2 bit upon overflow. The overflow
also causes the timer registers to be reloaded with the 16-bit value in RC2H and RC2L. The values
in RC2H and RC2L are preset by software.
If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at the
external input T2EX (P1.1). This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can
generate an timer 2 interrupt if enabled.
Setting the DCEN bit enables timer 2 to count up or down as shown in
figure
6-16
. In this mode the
T2EX pin controls the direction of count.
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