參數(shù)資料
型號(hào): QL12x16B
廠商: QuickLogic Corp.
英文描述: pASIC 1 Family ViaLink Technology Very-High-Speed CMOS FPGAs(pASIC 1系列 ViaLink技術(shù)超高速CMOS現(xiàn)場(chǎng)可編程門陣列)
中文描述: 帕希奇1家庭技術(shù)ViaLink?技術(shù)非常高速的CMOS的FPGA(帕希奇1系列技術(shù)ViaLink?技術(shù)超高速的CMOS現(xiàn)場(chǎng)可編程門陣列)
文件頁(yè)數(shù): 4/4頁(yè)
文件大?。?/td> 186K
代理商: QL12X16B
pASIC 1 Family
4-4
Three types of input and output structures are provided on pASIC 1
devices to configure buffering functions at the external pads. They are the
Bi-directional Input/Output (I/O) cell, the Dedicated Input (I) cell and the
Clock Input cell (I/CLK).
The bidirectional I/O cell, shown in Figure 3, consists of a 2-input OR gate
connected to a pin buffer driver. The buffer output is controlled by a three-state
enable line to allow the pad to also act as an input. The output may be
configured as active HIGH, active LOW, or as an open drain inverting buffer.
The Dedicated Input I cell, Figure 4, conveys true and complement
signals from the input pads into the array of logic cells. As these pads
have nearly twice the current drive capability of the I/O pads, they are
useful for distributing high fanout signals across the device. The Clock
Input I/CLK cell (Figure 5) drives a low-skew, fanout-independent clock
tree that can connect to the clock, set, or reset inputs of the flip-flop.
The pASIC 1 Family is based on a 0.65 micron high-volume CMOS
fabrication process with the ViaLink programmable-via antifuse
technology inserted between the metal deposition steps. Devices from this
base CMOS process have been qualified to meet the requirements of
MIL-STD-883D, Revision B.
FIGURE 2
pASIC 1 Internal
Logic Cell
FIGURE 3
Bidirectional I/O
Cell
FIGURE 4
Dedicated Input
High-Drive Cell
FIGURE 5
Clock Input Cell
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