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參數(shù)資料
| 型號： | QL16x24B |
| 廠商： | QuickLogic Corp. |
| 英文描述： | pASIC 1 Family ViaLink Technology Very-High-Speed CMOS FPGAs(pASIC 1系列 ViaLink技術(shù)超高速CMOS現(xiàn)場可編程門陣列) |
| 中文描述： | 帕希奇1家庭技術(shù)ViaLink？技術(shù)非常高速的CMOS的FPGA（帕希奇1系列技術(shù)ViaLink？技術(shù)超高速的CMOS現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 2/4頁 |
| 文件大小： | 186K |
| 代理商： | QL16X24B |
pASIC 1 Family
4-2
The pASIC 1 Family of very-high-speed CMOS user-programmable
ASIC (pASIC) devices is based on the first FPGA technology to combine
high speed, high density and low power in a single architecture. pASIC 1
devices range in density from 1,000 to 8,000 usable ASIC gates,
equivalent to 2,000 to 14,000 usable programmable (PLD) gates.
All pASIC 1 devices are based on an array of highly flexible logic cells
which have been optimized for efficient implementation of high-speed
arithmetic, counter, data path, state machine, random and glue logic
functions. Logic cells are configured and interconnected by rows and
columns of routing metal and ViaLink metal-to-metal programmable-via
interconnect elements.
ViaLink technology provides a nonvolatile, permanently programmed
custom logic function capable of operating at counter speeds of over 150
MHz. Internal logic cell nominal worst case delays are under 2 ns and
total input to output combinatorial logic delays are under 8 ns. This
permits high-density programmable devices to be used with today’s
fastest microprocessors, while consuming a fraction of the power and
board area of PAL/GAL, CPLD and discrete logic solutions.
Designs can be entered on PC or workstation platforms using either
QuickLogic’s Quick
Works
toolkit or a variety of popular third-party
design-entry, logic synthesis and simulation tools. The Quick
Works
toolkit provides design entry (VHDL, Verilog and schematic), place and
route, timing analysis, simulation and programming for all QuickLogic
devices. The pASIC 1 architecture provides sufficient on-chip routing to
allow fully automatic place and route of designs using up to 100% of the
available logic cells.
The pASIC 1 device architecture consists of an array of user-configurable
logic building blocks, called logic cells, set in a grid of metal wiring
channels similar to those of a gate array. Figure 1 shows a section of a
pASIC 1 device containing internal logic cells, input/output cells and
dual-layer vertical and horizontal metal routing channels. Through
ViaLink elements located at the wire intersections, the output of any cell
may be programmed to connect to the input of any other cell.
This regular and orthogonal interconnect makes the pASIC 1 architecture
similar in structure and performance to a metal masked gate array. Abundant
wiring resources permit 100% automatic placement and routing of designs
using up to 100% of the logic cells.
FAMILY
SUMMARY
pASIC 1
Architecture
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