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參數(shù)資料
| 型號： | QL5064-33BPB484C |
| 英文描述： | BUS CONTROLLER |
| 中文描述： | 總線控制器 |
| 文件頁數(shù)： | 13/37頁 |
| 文件大?。?/td> | 806K |
| 代理商： | QL5064-33BPB484C |
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QL5064 QuickPCI Data Sheet Rev D
13
QL5064 QuickPCI Data Sheet
14.0 RAM Module Features
Figure 8: RAM Module
The RAM modules are "dual-ported", with completely independent READ and WRITE ports and
separate READ and WRITE clocks. The READ ports support asynchronous and synchronous operation,
while the WRITE ports support synchronous operation. Each port has 18 data lines and 9 address lines,
allowing word lengths of up to 18 bits and address spaces of up to 512 words. Depending on the mode
selected, however, some higher order data or address lines may not be used.
The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read Enable
(RE) acts as a clock enable for synchronous READ operation (ASYNCRD input low), or as a flow-through
enable for asynchronous READ operation (ASYNCRD input high).
Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules
by connecting corresponding address lines together and dividing the words between modules. This
approach allows up to 512-deep configurations as large as 22 bits wide in the QL5064 device.
A similar technique can be used to create depths greater than 512 words. In this case address signals
higher than the eighth bit are encoded onto the write enable (WE) input for WRITE operations. The
READ data outputs are multiplexed together using encoded higher READ address bits for the multiplexer
SELECT signals.
MODE[1:0]
WA[a:0]
WD[w:0]
WE
WCLK
RAM Module
ASYNCRD
RA[a:0]
RD[w:0]
RE
RCLK
Mode:
64x18
[5:0]
[17:0]
128x9
[6:0]
[8:0]
256x4
[7:0]
[3:0]
512x2
[8:0]
[1:0]
Address Busses [a:0]
Data Busses [w:0]
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