參數(shù)資料
型號: QLU2108-PQ208C
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁數(shù): 12/22頁
文件大?。?/td> 195K
代理商: QLU2108-PQ208C
12
www.quicklogic.com
2001 QuickLogic Corporation
QLUX2108-PQ208C Device Data Sheet
7.1.2 Cell Level Transfer – Back to Back Cells
When, during a cell transfer, the Slave is able to receive a subsequent cell, the Master can
keep
ut_txenb
asserted between two cells
1
and asserts
ut_txsoc
, to start a new cell
transfer, immediately after the last octet of the previous cell
2
.
Figure 8: Back to Back Cell Transfer – Cell Level Transfer
7.2 Utopia Interface Single PHY Receive Interface (L1)
The Receive interface is controlled by the Master. The receive interface has data flowing
in the opposite direction to the Master enable
ut_rxenb
.
Receive data is transferred from the Slave to Master via the following procedure. The Slave
indicates it has valid data, then the Master asserts
ut_rxenb
to read this data from the
Slave. The Slave indicates valid data (thereby controlling the data flow) via the
ut_rxclav
signal.
7.2.1 Cell Level Transfer - Single Cell
The Slave asserts
ut_rx_clav
when it is ready to send a complete cell to the Master
device
1
. The Master interface asserts
ut_rxenb
to start the cell transfer. The Slave
samples
ut_rxenb
and starts driving data
2
. The Slave asserts
ut_rxsoc
together with
the cell first word to indicate the start of a cell
3
.
The Master can pause a transfer by de-asserting
ut_rxenb
4
. The Slave samples high
ut_rxenb
and stops driving data
5
. To resume the transfer, the Master re-asserts
ut_rxenb
6
. The Slave samples low
ut_rxenb
and starts driving valid data
7
.
The Master drives
ut_txenb
high one before the expected end of the current cell if the
Slave has no more cell to transfer
8
. The Slave de-asserts
ut_rxclav
to indicate that no
new cell is available
9
.
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