FN6979.1 November 19, 2009 Typical Application Reference Designs Figures 33 and 34 show reference design schematics for a QLx4600-S30 evaluatio" />
參數(shù)資料
型號: QLX4600SIQT7
廠商: Intersil
文件頁數(shù): 13/23頁
文件大?。?/td> 0K
描述: IC EQUALIZER REC 6.25GBPS 46QFN
標準包裝: 1
系列: QLx™
應用: 銅電纜模塊
電源電壓: 1.1 V ~ 1.3 V
封裝/外殼: 46-WFQFN 裸露焊盤
供應商設備封裝: 46-TQFN
包裝: 標準包裝
安裝類型: 表面貼裝
其它名稱: QLX4600SIQT7-DKR
QLX4600SIQT7-DKR-ND
QLX4600SIQT7DKR
20
FN6979.1
November 19, 2009
Typical Application Reference Designs
Figures 33 and 34 show reference design schematics for a QLx4600-S30 evaluation board with an SMA connector
interface. Figure 33 shows the schematic for the case when the equalizer boost level is set via the CP pins. Figure 34
shows the schematic for the case when the level is set via the serial bus interface.
FIGURE 33. APPLICATION CIRCUIT FOR THE QLx4600-S30 EVALUATION BOARD USING THE CONTROL PINS FOR
SETTING THE EQUALIZER COMPENSATION LEVEL
1
2
3
4
5
6
7
8
46
45
44
43
42
41
40
39
16
17
18
19
20
21
22
23
9
10
11
12
13
14
15
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
DI
DO
CP
3
[A
]
CP
3
[B
]
CP
3[
C
]
CP
4
[A
]
CP
4
[B
]
CP
4[
C
]
CL
K
EN
B
CP
1[
A
]
CP
1[
B
]
CP
1[
C]
CP
2[
A
]
CP
2[
B
]
CP
2[
C]
GND
IS2
IS1
MODE
IS4
IS3
1.2V
DT
IN1[P]
IN1[N]
IN2[P]
IN2[N]
IN3[P]
IN3[N]
IN4[P]
IN4[N]
OUT2[P]
OUT2[N]
OUT4[P]
OUT4[N]
OUT1[P]
OUT1[N]
OUT3[P]
OUT3[N]
6k
BGREF
A
QLx4600-S30
1.2V
100
pF
*
10
nF
Bypass circuit for each VDD pin: 4, 7, 10, 29, 32, 35
(*100pF capacitor should be positioned closest to the pin )
EQ Boost Control
for Channels 1 and 2
(See pages 15-17)
NC
Detection threshold
reference current
QLx4600-S30
LANE EXTENDER
Reference
Control Pin Mode
Quellan , Inc.
EQ Boost Control
for Channels 3 and 4
(See pages 15-17)
= SMA Connector
A) DC Blocking Capacitors = X7R or COG
0.1μF (>4GHz bandwidth)
Impedance Select (Channels 3 and 4)
Impedance Select (Channels 1 and 2)
MODE
MODE at 1.2V: Serial Control Mode
MODE at GND: Binary Control Mode
1.2V
10
0k
4
7nF
42
.2
k
QLx4600-S30
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