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參數(shù)資料
| 型號： | QLX4600SIQT7 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 8/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC EQUALIZER REC 6.25GBPS 46QFN |
| 標準包裝： | 1 |
| 系列： | QLx™ |
| 應(yīng)用： | 銅電纜模塊 |
| 電源電壓： | 1.1 V ~ 1.3 V |
| 封裝/外殼： | 46-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 46-TQFN |
| 包裝： | 標準包裝 |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | QLX4600SIQT7-DKR QLX4600SIQT7-DKR-ND QLX4600SIQT7DKR |
16
FN6979.1
November 19, 2009
Serial Bus Programming
Pins 16 (DI), 45 (ENB), and 46 (CLK) are used to
program the registers inside the QLx4600-S30. Figure 27
shows an exemplary timing diagram for the signals on
these pins. The serial bus can be used to program a
single QLx4600-S30 according to the following steps:
1. The ENB pin is pulled ‘LOW’.
- While this pin is ‘LOW’, the data input on DI are
read into registers but not yet latched.
- A setup time of tSCK is needed between ENB going
‘LOW’ and the first rising clock edge.
2. At least 21 values are read from DI on the rising
edge of the CLK signal.
- If more than 21 values are passed in, then only the
last 21 values are kept in a FIFO fashion.
- The data on DI should start by sending the value
destined for register 21 and finish by sending the
value destined for register 1.
- A range of clock frequencies can be used. A typical
rate is 10MHz. The clock should not exceed 20MHz.
-Setup (tSDI) and hold (tHDI) times are needed
around the rising clock edge.
3. The ENB pin is pulled ‘HIGH’ and the contents of the
registers are latched and take effect.
- After clocking in the last data bit, an additional
tHEN should elapse before pulling the ENB signal
‘HIGH’.
- After completing these steps, the new values will
affect within tD.
TABLE 4. DESCRIPTION OF INTERNAL SERIAL REGISTERS
REGISTER
EQUALIZER CHANNEL
DESCRIPTION
1
1-4
CP control override – Use registers 2 through 21 (rather than CP pins) to establish
the boost levels when this bit is set.
2
1
Equalizer setting bit 0 (LSB).
3
Equalizer setting bit 1.
4
Equalizer setting bit 2.
5
Equalizer setting bit 3.
6
Equalizer setting bit 4 (MSB).
7
2
Equalizer setting bit 0 (LSB).
8
Equalizer setting bit 1.
9
Equalizer setting bit 2.
10
Equalizer setting bit 3.
11
Equalizer setting bit 4 (MSB).
12
3
Equalizer setting bit 0 (LSB).
13
Equalizer setting bit 1.
14
Equalizer setting bit 2.
15
Equalizer setting bit 3.
16
Equalizer setting bit 4 (MSB).
17
4
Equalizer setting bit 0 (LSB).
18
Equalizer setting bit 1.
19
Equalizer setting bit 2.
20
Equalizer setting bit 3.
21
Equalizer setting bit 4 (MSB).
QLx4600-S30
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QLX4600-SL30 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad Lane Extender |
| QLZ06 0012-2513 | 制造商:ebm-papst Inc 功能描述: |
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| QLZ06 0600-2513 | 制造商:Ebm-Papst Industries 功能描述:Bulk |
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