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參數(shù)資料
| 型號(hào)： | QS5930 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| 中文描述： | 低偏移的CMOS PLL時(shí)鐘驅(qū)動(dòng)器，帶有集成環(huán)路濾波器 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 57K |
| 代理商： | QS5930 |
3
INDUSTRIAL TEMPERATURE RANGE
QS5930T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
NOTE:
1. Operation in the specified SYNC frequency range guarantees that the VCO will operate in its optimal range of 28MHz to F
MAX_Q
x2. Operation with
Sync inputs outside specified frequency ranges may result in out-of-lock outputs. FREQ_SEL only affects VCO frequency and does not affect output
frequencies.
FREQUENCY S ELECT ION T ABLE
Output Used for
Feedback
Q/2
Q
0
-Q
4
Q/2
Q
0
-Q
4
SYNC (MHz)
(allowable range)
(1)
Output Frequency Relationships
Q/2
SYNC
SYNC / 2
SYNC
SYNC / 2
FREQ_SEL
HIGH
HIGH
LOW
LOW
Mn.
14
28
7
14
Max
Q
0
- Q
4
SYNC X 2
SYNC
SYNC X 2
SYNC
F
MAX _Q/2
F
MAX _Q
F
MAX _Q/2
/2
F
MAX _Q
/2
DC ELECT RICAL CHARACT ERIS T ICS OV E R OPERAT ING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, AV
DD
/V
DD
= 5V ± 5%
Symbol
V
IH
V
IL
V
OH
Parameter
Conditions
Mn.
2
—
2.4
3
—
—
—
Typ.
—
—
—
—
—
—
—
Max.
—
0.8
—
—
0.55
0.2
5
Unit
V
V
V
V
V
V
μ
A
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
I
OH
=
24mA
I
OH
=
100
μ
A
V
DD
= Mn., I
OL
= 24mA
V
DD
= Mn., I
OL
= 100
μ
A
V
OUT
= V
DD
or GND,
V
DD
= Max., Outputs Disabled
AV
DD
= Max., V
IN
= AV
DD
or GND
V
OL
Output LOW Voltage
I
OZ
Output Leakage Current
I
IN
Input Leakage Current
—
—
5
μ
A
POWER S UPPLY CHARACT ERIS T ICS
Symbol
I
DDQ
Parameter
Test Conditions
Typ.
—
Max.
1
Unit
mA
Quiescent Power Supply Current
V
DD
= Max., OE/
RST
= LOW,
SYNC = LOW, All outputs unloaded
V
DD
= Max., V
IN
= 3V
V
DD
= Max., C
L
= 0pF
I
DD
I
DDD
Power Supply Current per Input HIGH
Dynamc Power Supply Current
1
30
0.3
μ
A
0.2
mA/MHz
INPUT T IMING REQUIRE MENT S
Symbol
t
R
, t
F
F
I
t
PWC
D
H
Description
(1)
Mn.
—
7
2
25
Max.
3
F
MAX _Q
—
75
Unit
ns
MHz
ns
%
Maximuminput rise and fall times, 0.8V to 2V
Input Clock Frequency, SYNC
(1)
Input clock pulse, HIGH or LOW
(2)
Duty Cycle, SYNC
(2)
NOTES:
1. See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with
different FEEDBACK and FREQ_SEL combinations.
2. Where pulse witdh implied by D
H
is less than t
WPC
limit, t
WPC
limit applies
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