參數(shù)資料
型號： R5F562N7ADFP#V0
廠商： Renesas Electronics America
文件頁數(shù)： 29/148頁
文件大?。?/td> 0K
描述： MCU 32BIT FLASH 384KROM 100LQFP
產(chǎn)品培訓(xùn)模塊： RX Compare Match Timer
RX DMAC
標(biāo)準(zhǔn)包裝： 1
系列： RX600
核心處理器： RX
芯體尺寸： 32-位
速度： 100MHz
連通性： EBI/EMI，I²C，SCI，SPI，USB
外圍設(shè)備： DMA，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 72
程序存儲器容量： 384KB（384K x 8）
程序存儲器類型： 閃存
RAM 容量： 64K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10/12b，D/A 1x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤
PIC18F6520/8520/6620/8620/6720/8720
DS39609B-page 122
2004 Microchip Technology Inc.
10.8
PORTH, LATH and TRISH
Registers
PORTH is an 8-bit wide, bidirectional I/O port. The cor-
responding data direction register is TRISH. Setting a
TRISH bit (= 1) will make the corresponding PORTH
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISH bit (= 0)
will make the corresponding PORTH pin an output (i.e.,
put the contents of the output latch on the selected pin).
Read-modify-write operations on the LATH register,
read and write the latched output value for PORTH.
Pins RH7:RH4 are multiplexed with analog inputs
AN15:AN12. Pins RH3:RH0 are multiplexed with the
system bus as the external memory interface; they are
the high-order address bits, A19:A16. By default, pins
RH7:RH4 are enabled as A/D inputs and pins
RH3:RH0 are enabled as the system address bus.
Register ADCON1 configures RH7:RH4 as I/O or A/D
inputs. Register MEMCON configures RH3:RH0 as I/O
or system bus pins.
EXAMPLE 10-8:
INITIALIZING PORTH
FIGURE 10-17:
RH3:RH0 PINS BLOCK
DIAGRAM IN I/O MODE
FIGURE 10-18:
RH7:RH4 PINS BLOCK
DIAGRAM IN I/O MODE
Note:
PORTH is available only on PIC18F8X20
devices.
Note 1: On
Power-on
Reset,
PORTH
pins
RH7:RH4 default to A/D inputs and read
as ‘0’.
2: On
Power-on
Reset,
PORTH
pins
RH3:RH0 default to system bus signals.
CLRF
PORTH
; Initialize PORTH by
; clearing output
; data latches
CLRF
LATH
; Alternate method
; to clear output
; data latches
MOVLW
0Fh
;
MOVWF
ADCON1
;
MOVLW
0CFh
; Value used to
; initialize data
; direction
MOVWF
TRISH
; Set RH3:RH0 as inputs
; RH5:RH4 as outputs
; RH7:RH6 as inputs
Data
Bus
WR LATH
WR TRISH
RD PORTH
Data Latch
TRIS Latch
RD TRISH
Schmitt
Trigger
Input
Buffer
I/O pin(1)
Q
D
CK
Q
D
CK
EN
QD
EN
RD LATH
or
PORTH
Note 1: I/O pins have diode protection to VDD and VSS.
Data
Bus
WR LATH
WR TRISH
RD PORTH
Data Latch
TRIS Latch
RD TRISH
Schmitt
Trigger
Input
Buffer
I/O pin(1)
Q
D
CK
Q
D
CK
EN
QD
EN
RD LATH
or
PORTH
To A/D Converter
Note 1: I/O pins have diode protection to VDD and VSS.
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