參數(shù)資料
型號: R5F562N8ADBG#U0
廠商: Renesas Electronics America
文件頁數(shù): 111/148頁
文件大?。?/td> 0K
描述: MCU 32BIT FLASH 512KROM 176LFBGA
產(chǎn)品培訓模塊: RX Compare Match Timer
RX DMAC
標準包裝: 1
系列: RX600
核心處理器: RX
芯體尺寸: 32-位
速度: 100MHz
連通性: EBI/EMI,I²C,SCI,SPI,USB
外圍設(shè)備: DMA,LVD,POR,PWM,WDT
輸入/輸出數(shù): 126
程序存儲器容量: 512KB(512K x 8)
程序存儲器類型: 閃存
RAM 容量: 96K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10/12b,D/A 2x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 176-LFBGA
包裝: 托盤
2004 Microchip Technology Inc.
DS39609B-page 63
PIC18F6520/8520/6620/8620/6720/8720
REGISTER 5-1:
EECON1 REGISTER (ADDRESS FA6h)
R/W-x
U-0
R/W-0
R/W-x
R/W-0
R/S-0
EEPGD
CFGS
FREE
WRERR
WREN
WR
RD
bit 7
bit 0
bit 7
EEPGD: Flash Program or Data EEPROM Memory Select bit
1
= Access Flash program memory
0
= Access data EEPROM memory
bit 6
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1
= Access configuration registers
0
= Access Flash program or data EEPROM memory
bit 5
Unimplemented: Read as ‘0’
bit 4
FREE: Flash Row Erase Enable bit
1
= Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0
= Perform write only
bit 3
WRERR: Flash Program/Data EEPROM Error Flag bit
1
= A write operation is prematurely terminated
(any Reset during self-timed programming in normal operation)
0
= The write operation completed
Note:
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows
tracing of the error condition.
bit 2
WREN: Flash Program/Data EEPROM Write Enable bit
1
= Allows write cycles to Flash program/data EEPROM
0
= Inhibits write cycles to Flash program/data EEPROM
bit 1
WR: Write Control bit
1
= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write
cycle. (The operation is self-timed and the bit is cleared by hardware once write is
complete. The WR bit can only be set (not cleared) in software.)
0
= Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1
= Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit
can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)
0
= Does not initiate an EEPROM read
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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