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參數(shù)資料
| 型號(hào)： | RDC-19222-202 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 1233K |
| 代理商： | RDC-19222-202 |
15
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
V-12/08-0
DATA
VALID
300 ns max
INHIBIT
100 ns MAX
ENABLE
150 ns MAX
DATA
VALID
HIGH Z
Note: For 16 BIT BUS operation, EM/EL may be tied to ground
for transparent mode, as long as only 1 R/D channel is on
the data bus.
1/ (40 x F )
S
(375 nsec nominal)
CB
50 ns
DATA
VALID
DATA
VALID
*
* Next CB pulse cannot occur for a minimum of 150 nsec.
FIGURE 13. INHIBIT TIMING
FIGURE 14. ENABLE TIMING
FIGURE 15. cONVERTER BUsY TIMING
The Inhibit (INH) signal is used to freeze the digital output angle
in the transparent output data latch while data is being trans-
ferred. Application of an Inhibit signal does not interfere with the
continuous tracking of the converter. As shown in FIguRE 13,
angular output data is valid 300 ns maximum after the applica-
tion of the negative inhibit pulse.
Output angle data is enabled onto the tri-state data bus in two
bytes. Enable MSBs (EM) is used for the most significant 8 bits
and Enable LSBs (EL) is used for the least significant 8 bits. As
shown in FIguRE 14, output data is valid 150 ns maximum after
the application of a negative enable pulse. The tri-state data bus
returns to the high impedance state 100 ns maximum after the
rising edge of the enable signal.
The Converter Busy (CB) signal indicates that the tracking con-
verter output angle is changing 1 LSB. As shown in FIguRE 15,
output data is valid 50 ns maximum after the middle of the CB
pulse. CB pulse width is 1/(40 x Fs), which is nominally 375 ns.
Note: The converter INH may be applied regardless of the CB
line state. If the CB is busy the converter INH will wait for
the timing to CB “Figure 15” before setting the INH latch.
Therefore, there is no need to monitor the CB line when
applying an inhibit signal to the converter.
BuILT-IN-TEST (BIT)
The Built-ln-Test output (BIT) monitors the level of error from the
demodulator. This signal is the difference in the input and output
angles and ideally should be zero. However, if it exceeds approx-
imately 100 LSBs (of the selected resolution) the logic level at
BIT will change from a logic 1 to a logic 0.
A 500ms delay occurs before the excessive error bit becomes
active. The dynamic delay is responsive to the active filler loop.
This condition will occur during a large step and reset after the
converter settles out. BIT will also change to logic 0 for an over-
velocity condition, because the converter loop cannot maintain
input/output or if the converter malfunctions where it cannot
maintain the loop at a null.
BIT will also be set low for a detected total Loss-of-Signal (LOS).
The BIT signal may pulse during certain error conditions (i.e.,
converter spin around or signal amplitude on threshold of LOS).
LOS will be detected if both sin and cos input voltages are less
than 800 mV peak. The LOS has a filter on it to filter out the
reference. Since the lowest specified frequency is 47hz (-27ms)
the filter must have a time constant long enough to filter this out.
Time constants of 50ms or more are possible.
ENCODER EMuLATION
The RDC-19220 series can be made to emulate incremental
optical encoder output signals, where such an interface is
desired. This is accomplished by tying EL to -5 V, whereby CB
becomes Zero Index (Zl) Logic 1 at all 0s, the LSB+1 becomes
A, and the exclusive-or of the LSB and LSB+1 becomes B emu-
lating A QuAD B signals as illustrated in FIguRE 16A. Also, the
LSB byte is always enabled.
FIguRE 16B illustrates a more detailed circuit with delays and
filtering to eliminate potential glitch due to data skew and rise/fall
differences caused by logic loading.
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