參數(shù)資料
型號: RF133
英文描述: RF/IF Transceiver For GSM Applications
中文描述: 射頻/中頻收發(fā)器的GSM應(yīng)用
文件頁數(shù): 3/17頁
文件大?。?/td> 123K
代理商: RF133
RF/IF Transceiver
RF133
100776A
Conexant
3
Proprietary Information and Specifications are Subject to Change
October 8, 1999
Table 1. RF133 Signal Descriptions
Pin #
Name
Description
Pin #
Name
Description
1
GND
Ground (Tx phase detector/charge pump)
25
VCC
Supply (2
nd
LO output buffers)
2
TLCPO
Translation loop charge pump output
26
LPFADJ
Adjustment pin for baseband low pass filter corner
frequency
3
VCC
Supply (phase detector and charge pump)
27
VCC
Supply (2
nd
LO)
4
VCC
Supply (Tx modulator, Rx baseband sections)
28
RES1
Resonator pin
5
GND
Ground (Tx modulator, Rx baseband sections)
29
RES2
Resonator pin
6
TXIFIN+
Tx IF input
30
VCC
Supply (2
nd
LO)
7
TXIFIN–
Tx IF input
31
GND
Ground (2
nd
LO)
8
GND
Ground
32
BPC
Bypass capacitor
9
TXI+
Tx modulator input
33
SXENA
Synthesizer enable
10
TXI–
Tx modulator input
34
RXIFF–
Rx IF filter pin
11
TXQ+
Tx modulator input
35
RXIFF+
Rx IF filter pin
12
TXQ–
Tx modulator input
36
DATA
Data input
13
TXMO+
Tx modulator output
37
CLK
Clock input
14
TXMO–
Tx modulator output
38
LE
Latch enable input
15
RXI+
Rx baseband output
39
RXENA
Receiver enable
16
RXI–
Rx baseband output
40
RXIFIN–
Rx IF input
17
RXQ+
Rx baseband output
41
RXIFIN+
Rx IF input
18
RXQ–
Rx baseband output
42
GND
Ground (Tx mxer, Rx IF sections)
19
T/H
Track and hold signal
43
LO1IN–
1
st
local oscillator input
20
CTH1
Capacitor for track and hold
44
LO1IN+
1
st
local oscillator input
21
CTH2
Capacitor for track and hold
45
VCC
Supply (Tx mxer, Rx IF sections)
22
GND
Ground (2
nd
LO output buffers)
46
TXRFIN–
Transmt RF input
23
LO2O+
2
nd
local oscillator output
47
TXRFIN+
Transmt RF input
24
LO2O–
2
nd
local oscillator output
48
TXENA
Transmt enable
Technical Description
The RF 133 RF/IF transceiver unit is comprised of a receive
path, a transmt path, and a synthesizer section as shown in
Figure 2. The receive path consists of a selectable gain IF
chain, a quadrature demodulator, and baseband amplifier
circuitry with I and Q outputs. The transmt path is essentially an
I/Q modulator with a translation loop for frequency up-
conversion. An on-chip oscillator and frequency dividers make
up the synthesizer section. Each section of the RF 133 is
separately enabled via the enable signals: TXENA, RXENA, and
SXENA.
To control different modes of operation, a serial 21-bit word (bits
S1 to S21) is written to the on-chip registers. This 21-bit word is
programmed using the three-wire input signals, CLK, DATA, and
LE. To ensure that the data remains latched, either one of the
signals TXENA, RXENA, or SXENA must stay enabled. The
operating mode that draws the least current (12 mA) is the
synthesizer mode (i.e., the mode that results when only SXENA
is enabled) (refer to Table 5). In the sleep mode, the device
typically draws less than 1
μ
A of current.
The block diagramin Figure 3 shows a complete RF/IF dual-
band transceiver chipset using the RF133.
Receive Path _______________________________________
Selectable Gain IF Chain and Quadrature Mxer
. The receive
path of the RF133 is composed of an IF section and a baseband
section. The IF section consists of three programmable gain
amplifiers: PGA, PGB, and PGC.
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