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參數(shù)資料
| 型號： | RF133 |
| 英文描述： | RF/IF Transceiver For GSM Applications |
| 中文描述： | 射頻/中頻收發(fā)器的GSM應(yīng)用 |
| 文件頁數(shù)： | 4/17頁 |
| 文件大小： | 123K |
| 代理商： | RF133 |
RF133
RF/IF Transceiver
4
October 8, 1999
Conexant
100776A
Proprietary Information and Specifications are Subject to Change
PFD
CHP
3 Wire
Bias
DC
OC
PGB
PGA
PGC
PGD
PGD
DUAL PLL
Combiner
CTH1
CTH2
LOOP FILTER
TX DCS VCO
TX GSM VCO
TX ENA
T/H
RX ENA
SX ENA
RXI
RXQ
TXI
TXQ
CLK
LE
DATA
C453
LPF
LPF
TX IF FILTER
90
90
÷
2
÷
4
÷
2
÷
4
÷
1
÷
2
÷
1
÷
2
÷
2
÷
4
RF210
LNA/Image Reject Mixer
IF SAW
Filter
Tx/Rx VCO
UHF VCO
GSM
Rx Filter
DCS
Rx Filter
RF133
Tx/Rx VCO
T
LC
Tank
Diplexer
Coupler
T/R
Antenna
RM008
RF142
VAPC
T/R
Figure 3. Dual-Band Transceiver Chipset Using The RF133
PGA has two gain settings, either 0 dB or 20 dB, whereas both
PGB and PGC have a gain range of -10 dB to 20 dB
programmable in 2 dB steps. The output of PGC is fed to a
quadrature mxer. The quadrature mxer has a fixed conversion
gain of 10 dB and its LO inputs are taken fromthe outputs of a
quadrature divider (divide by 2 or 4).
Baseband Integrated Filters, Baseband Amplifiers, and DC
Offset Compensation
. Immediately following the quadrature
mxer (demodulator) is the baseband section (DC offset
compensation circuitry, two integrated baseband filters and two
programmable gain amplifiers). Each programmable gain
amplifier in the baseband section, both labelled PGD, has four
different gain settings: 0 dB, 10 dB, 20 dB, or 30 dB.
The corner frequency of the integrated baseband filters is
adjustable by using an appropriate value resistor at pin 26,
LPFADJ. At the nomnal cutoff frequency of 105 kHz, the
resistor value is 75.1 k
.
Due to possible high gain of the baseband amplifiers (PGD), any
DC offsets at the outputs of the quadrature mxer are amplified
and, if uncorrected, the I and Q outputs can suffer from
significant unwanted DC offset voltages. To cancel out these
effects, the RF133 must be calibrated.
During compensation, the correction voltages are stored in
external hold capacitors CTH1 and CTH2, then the loop is
opened immediately thereafter. The corrected I and Q outputs
are then fed directly to external circuitry for further baseband
processing.
The timng diagramfor this calibration sequence in reference to
the receive slot is shown in Figure 4 (the front-end mxer is
assumed to be Rockwell’s RF210 dual-band, image reject
downconverter). At first, the RF133 receiver is turned on
(RXENA is high). After time T1, the track and hold signal, T/H,
places the DC compensation circuitry in the track mode for time
T2. Then, there is a settling time, T3, before the external front-
end is turned on. Finally, the front-end must be turned on for
time T4 before the receive slot.
Time T2 can vary from10
μ
sec to 350
μ
sec. This duration is
dependent on 1) the value of the hold capacitors (CTH1 and
CTH2), and 2) whether the calibration is done fromframe to
frame or froma cold start. This is tabulated in Table 2.
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