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參數資料
| 型號： | RH80532NC021256 |
| 元件分類： | 微處理器 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數： | 18/93頁 |
| 文件大?。?/td> | 2353K |
| 代理商： | RH80532NC021256 |
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Mobile Intel
Pentium
4 Processor-M
18
Datasheet
250686-002
For reliable operation, always connect unused inputs or bidirectional signals that are not terminated
on the die to an appropriate signal level. Note that on-die termination has been included on the
Mobile Intel Pentium 4 Processor-M to allow signals to be terminated within the processor silicon.
Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is provided on
the processor silicon.
Table 3
lists details on AGTL+ signals that do not include on-die termination.
Unused active high inputs should be connected through a resistor to ground (V
SS
). Refer to the
Mobile Intel
Pentium
4 Processor-M and Intel
845MP/845MZ Chipset Platform Design Guide
for the appropriate resistor values.
Unused outputs can be left unconnected, however, this may interfere with some TAP functions,
complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying
bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will
also allow for system testability. For unused AGTL+ input or I/O signals that don’t have on-die
termination, use pull-up resistors of the same value in place of the on-die termination resistors
(R
TT
). See
Table 17
.
The TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die
termination. Inputs and used outputs must be terminated on the system board. Unused outputs may
be terminated on the system board or left unconnected. Note that leaving unused outputs
unterminated may interfere with some TAP functions, complicate debug probing, and prevent
boundary scan testing. Signal termination for these signal types is discussed in the
Mobile Intel
Pentium
4 Processor-M and Intel
845MP/845MZ Chipset Platform Design Guide
. TAP signal
termination requirements are also discussed in
ITP700 Debug Port Design Guide
.
The TESTHI pins should be tied to the processor V
CC
using a matched resistor, where a matched
resistor has a resistance value within + 20% of the impedance of the board transmission line traces.
For example, if the trace impedance is 50
, then a value between 40
and 60
is required.
The TESTHI pins may use individual pull-up resistors or be grouped together as detailed below. A
matched resistor should be used for each group:
1.TESTHI[1:0]
2.TESTHI[5:2]
3.TESTHI[10:8]
Additionally, if the ITPCLKOUT[1:0] pins are not used then they may be connected individually to
V
CC
using matched resistors or grouped with TESTHI[5:2] with a single matched resistor. If they
are being used, individual termination with 1-k
resistors is required. Tying ITPCLKOUT[1:0]
directly to V
CC
or sharing a pull-up resistor to V
CC
will prevent use of debug interposers. This
implementation is strongly discouraged for system boards that do not implement an onboard debug
port.
As an alternative, group 2 (TESTHI[5:2]), and the ITPCLKOUT[1:0] pins may be tied directly to
the processor V
CC
. This has no impact on system functionality. TESTHI[0] may also be tied
directly to processor V
CC
if resistor termination is a problem, but matched resistor termination is
recommended. In the case of the ITPCLKOUT[1:0] pins, direct tie to V
CC
is strongly discouraged
for system boards that do not implement an onboard debug port.
Tying any of the TESTHI pins together will prevent the ability to perform boundary scan testing.
Pullup/down resistor requirements for the VID[4:0] and BSEL[1:0] signals are included in the
signal descriptions in Section 5.
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