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參數(shù)資料
| 型號： | RH80532NC029256 |
| 元件分類： | 微處理器 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 33/93頁 |
| 文件大?。?/td> | 2353K |
| 代理商： | RH80532NC029256 |
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Mobile Intel
Pentium
4 Processor-M
250686-002
Datasheet
33
Figure 7. ITPCLKOUT[1:0] Output Buffer Diagram
NOTES:
1. See
Table 15
for range of Ron.
2. The Vcc referred to in this figure is the instantaneous Vcc.
3. Refer to the
ITP700 Debug Port Design Guide
and the appropriate platform design guidelines for the value of
Rext.
Table 16. BSEL [1:0] and VID[4:0] DC Specifications
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These parameters are not tested and are based on design simulations.
3. Leakage to Vss with pin held at 2.50 V.
2.12
AGTL+ System Bus Specifications
Routing topology recommendations may be found in the
Mobile Intel
Pentium
4 Processor-M
and Intel
845MP/845MZ Chipset Platform Design Guide.
Termination resistors are not required
for most AGTL+ signals, as these are integrated into the processor silicon.
Valid high and low levels are determined by the input buffers which compare a signal’s voltage
with a reference voltage called GTLREF (known as V
REF
in previous documentation).
Table 17
lists the GTLREF specifications. The AGTL+ reference voltage (GTLREF) should be
generated on the system board using high precision voltage divider circuits. It is important that the
system board impedance is held to the specified tolerance, and that the intrinsic trace capacitance
Vcc
Ron
Processor Package
Rext
To Debug Port
Symbol
Parameter
Min
Max
Unit
Notes
1
Ron
(BSEL)
Buffer On Resistance
9.2
14.3
2
Ron
(VID)
Buffer On Resistance
7.8
12.8
2
I
HI
Pin Leakage Hi
N/A
100
μA
3
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相關代理商/技術參數(shù) |
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| RH80532NC033256 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
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| RH80532NC049256S L8SB | 制造商:Intel 功能描述:INTEL CELERON PROCESSOR AVAILABLE AT 1.60 GHZ, 1.8 GHZ, 2.00 GHZ, 2.2 GHZ |
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