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參數(shù)資料
| 型號： | RHF1401KSO-01V |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | ADC |
| 英文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO48 |
| 封裝： | HERMETIC SEALED, SOP-48 |
| 文件頁數(shù)： | 33/34頁 |
| 文件大小： | 1474K |
| 代理商： | RHF1401KSO-01V |
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Timing characteristics
RHF1401
8/34
Doc ID 13317 Rev 5
5
Timing characteristics
Figure 11.
Timing diagram
The input signal is sampled on the rising edge of the clock while the digital outputs are
synchronized on the falling edge of the clock. The duty cycles on DR and CLK are the same.
Table 2.
Timing characteristics
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
DC
Clock duty cycle
Fs = 20 Msps
45
50
65
%
Tod
Data output delay (fall of
clock to data valid) (1)
1.
As per Figure 11.
10 pF load capacitance
5
7.5
13
ns
Tpd
Data pipeline delay(2)
2.
If the duty cycle does not equal 50%: Tpd = 7 cycles + CLK pulse width.
Duty cycle = 50%
7.5
cycles
Ton
Falling edge of OEB to
digital output valid data
1ns
Toff
Rising edge of OEB to
digital output tri-state
1ns
TrD
Data rising time
10 pF load capacitance
6
ns
TfD
Data falling time
10 pF load capacitance
3
ns
N-2
N-1
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N-8
N-7
N -6
N
N-5
N -4
N+1
N-3
N-1
HZ state
Analog
input
CLK
OEB
Data
output
DR
Toff
Ton
Tpd +Tod
Tod
AM06120
OR
Tod
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