參數(shù)資料
型號: RM7000-200S
廠商: PMC-Sierra, Inc.
英文描述: RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released
中文描述: RM7000⑩微處理器與片上二級高速緩存數(shù)據(jù)發(fā)布
文件頁數(shù): 7/54頁
文件大?。?/td> 901K
代理商: RM7000-200S
RM7000A
Microprocessor with On-Chip Secondary Cache Datasheet
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
s Internal Use
Document ID: PMC-2002175, Issue 1
7
Released
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10 Processor Block Write ..............................................................................................31
Figure 11 Multiple Outstanding Reads ......................................................................................31
Figure 12 Clock Timing .............................................................................................................49
Figure 13 Input Timing ..............................................................................................................49
Figure 14 Output Timing ...........................................................................................................49
Block Diagram ..........................................................................................................10
CP0 Registers ...........................................................................................................12
Instruction Issue Paradigm .......................................................................................13
Pipeline 1...................................................................................................................4
CP0 Registers ...........................................................................................................18
Kernel Mode Virtual Addressing (32-bit mode) .........................................................19
Tertiary Cache Hit and Miss .....................................................................................25
Typical Embedded System Block Diagram ...............................................................28
Processor Block Read ..............................................................................................30
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