參數資料
型號： RM7000-266T
廠商： PMC-SIERRA INC
元件分類： 微控制器/微處理器
英文描述： RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released
中文描述： 64-BIT, 266 MHz, RISC PROCESSOR, PBGA304
封裝： 31 X 31 MM, TBGA-304
文件頁數： 41/54頁
文件大?。?/td> 901K
代理商： RM7000-266T
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002175, Issue 1
41
RM7000
Microprocessor with On-Chip Secondary Cache Datasheet
Released
Table 19
Tertiary cache interfacePins
Pin Name
Type
TcCLR*
Output
Description
Tertiary Cache Block Clear
Requests that all valid bits be cleared in the Tag RAMs. Many RAM
’
s
may not support a block clear therefore the block clear capability is not
required for the cache to operate.
Tertiary Cache Write Enable
Asserted to cause a write to the cache. Two identical signals are
provided to balance the capacitive load relative to the remaining cache
interface signals.
Tertiary Cache Data RAM Chip Enable
When asserted this signal causes the data RAM
’
s to read out their
contents. Two identical signals are provided to balance the capacitive
load relative to the remaining cache interface signals
Tertiary Cache Data RAM Output Enable
When asserted this signal causes the data RAM
’
s to drive data onto
their I/O pins. This signal is monitored by the processor to determine
when to drive the data RAM write enable in a tertiary cache miss refill
sequence.
Tertiary Cache Line Index
Tertiary Cache Tag Match
This signal is asserted by the cache Tag RAM
’
s when a match occurs
between the value on its data inputs and the contents of the addressed
location in the RAM.
Tertiary Cache Tag RAM Chip Enable
When asserted this signal will cause either a probe or a write of the Tag
RAM
’
s depending on the state of the Tag RAM
’
s write enable signal.
This signal is monitored by the external agent and indicates to it that a
tertiary cache access is occurring.
Tertiary Cache Tag RAM Data Enable
When asserted this signal causes the value on the data inputs of the
Tag RAM to be latched into the RAM. If a refill of the RAM is necessary,
this latched value will be written into the Tag RAM array. Latching the
Tag allows a shared address/data bus to be used without incurring a
penalty to re-present the Tag during the refill sequence.
Tertiary Cache Tag RAM Output Enable
When asserted this signal causes the Tag RAM
’
s to drive data onto
their I/O pins.
Tertiary Cache Double Word Index
Driven by the processor on cache hits and by the external agent on
cache miss refills.
Tertiary Cache Valid
This signal is driven by the processor as appropriate to make a cache
line valid or invalid. On Tag read operations the Tag RAM will drive this
signal to indicate the line state.
TcCWE*(1:0)
Output
TcDCE*(1:0)
Output
TcDOE*
Input
TcLine(17:0)
TcMatch
Output
Input
TcTCE*
Output
TcTDE*
Output
TcTOE*
Output
TcWord(1:0)
Input/Output
TcValid
Input/Output
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相關代理商/技術參數
參數描述
RM7000-300T 制造商:QED 功能描述: 制造商:QED 功能描述:Microprocessor, 64 Bit, 304 Pin, Plastic, BGA
RM7000A 制造商:PMC 制造商全稱:PMC 功能描述:64-Bit MIPS RISC Microprocessor with Integrated L2 Cache
RM7000A-300T 制造商:Quantum Effect Devices 功能描述:64-BIT, 300 MHz, MICROPROCESSOR, 304 Pin Plastic BGA
RM7000A-350T 制造商:PMC-Sierra 功能描述:Microprocessor, 64 Bit, 304 Pin, Plastic, BGA
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