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參數(shù)資料
| 型號： | RM7000-266T |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| 中文描述： | 64-BIT, 266 MHz, RISC PROCESSOR, PBGA304 |
| 封裝： | 31 X 31 MM, TBGA-304 |
| 文件頁數(shù)： | 9/54頁 |
| 文件大?。?/td> | 901K |
| 代理商： | RM7000-266T |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002175, Issue 1
9
RM7000
Microprocessor with On-Chip Secondary Cache Datasheet
Released
1
Features
Dual Issue symmetric superscalar microprocessor with instruction prefetch optimized for
system level price/performance
200, 250, 266, 300 MHz operating frequency
>500 Dhrystone 2.1 MIPS @ 300 MHz
High-performance system interface
1000 MB per second peak throughput
125 MHz max. freq., multiplexed address/data
Supports two outstanding reads with out-of-order return
Processor clock multipliers 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9
Integrated primary and secondary caches
—
all are 4-way set associative with 32 byte line size
16 KB instruction, 16 KB data, 256 KB on-chip secondary
Per line cache locking in primaries and secondary
Fast Packet Cache
increases system efficiency in
networking applications
Integrated external cache controller (up to 8 MB)
High-performance floating-point unit
—
600 MFLOPS maximum
Single cycle repeat rate for common single-precision operations and some double-pre-
cision operations
Single cycle repeat rate for single-precision combined multiply-add operations
Two cycle repeat rate for double-precision multiply and double-precision combined
multiply-add operations
MIPS IV Superset Instruction Set Architecture
Data
PREFETCH
instruction allows the processor to overlap cache miss latency and
instruction execution
Single-cycle floating-point multiply-add
Integrated memory management unit
Fully associative joint TLB (shared by I and D translations)
64/48 dual entries map 128/96 pages
Variable page size
Embedded application enhancements
Specialized DSP integer Multiply-Accumulate instructions, (
MAD
/
MADU
) and three-
operand multiply instruction (
MUL
)
I&D Test/Break-point (Watch) registers for emulation & debug
Performance counter for system and software tuning & debug
Fourteen fully prioritized vectored interrupts - 10 external, 2 internal, 2 software
Fully static CMOS design with dynamic power down logic
RM5271 pin compatible, 304 pin TBGA package, 31x31 mm
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| RM7000-300T | 制造商:QED 功能描述: 制造商:QED 功能描述:Microprocessor, 64 Bit, 304 Pin, Plastic, BGA |
| RM7000A | 制造商:PMC 制造商全稱:PMC 功能描述:64-Bit MIPS RISC Microprocessor with Integrated L2 Cache |
| RM7000A-300T | 制造商:Quantum Effect Devices 功能描述:64-BIT, 300 MHz, MICROPROCESSOR, 304 Pin Plastic BGA |
| RM7000A-350T | 制造商:PMC-Sierra 功能描述:Microprocessor, 64 Bit, 304 Pin, Plastic, BGA |
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