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參數(shù)資料
| 型號： | RM7000-300T |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| 中文描述： | 64-BIT, 300 MHz, RISC PROCESSOR, PBGA304 |
| 封裝： | 31 X 31 MM, TBGA-304 |
| 文件頁數(shù)： | 36/54頁 |
| 文件大小： | 901K |
| 代理商： | RM7000-300T |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002175, Issue 1
36
RM7000
Microprocessor with On-Chip Secondary Cache Datasheet
Released
Table 11 Cause Register
Table 12 Interrupt Control Register
Table 13 IPLLO Register
Table 14 IPLHI Register
These two registers contain a four-bit field corresponding to each interrupt thereby allowing each
interrupt to be programmed with a priority level from 0 to 13 inclusive. The priorities can be set in
any manner including having all the priorities set exactly the same. Priority 0 is the highest level
and priority 15 the lowest. The format of the priority level registers is shown in Table 13 and Table
14 above. The priority level registers are located in the coprocessor 0 control register space. For
further details about the control space see the section describing coprocessor 0.
In addition to programmable priority levels, the RM7000 also permits the spacing between
interrupt vectors to be programmed. For example, the minimum spacing between two adjacent
vectors is 0x20 while the maximum is 0x200. This programmability allows the user to either set up
the vectors as jumps to the actual interrupt routines or, if interrupt latency is paramount, to include
the entire interrupt routine at the vector. Table 15 illustrates the complete set of vector spacing
selections along with the coding as required in the
Interrupt Control
register bits 4:0.
In general, the active interrupt priority combined with the spacing setting generates a vector offset
which is then added to the interrupt base address of 0x200 to generate the interrupt exception
offset. This offset is then added to the exception base to produce the final interrupt vector address.
31
BD
30
0
29,28
CE
27
0
26
W2
25
W1
24
IV
23..8
IP[15..0]
7
0
6..2
EXC
0,1
0
31..16
0
15..8
IM[15..8]
7
TE
6..5
0
4..0
Spacing
31..28
IPL7
27..24
IPL6
23..20
IPL5
19..16
IPL4
15..12
IPL3
11..8
IPL2
7..4
IPL1
3..0
IPL0
31..28
0
27..24
0
23..20
IPL13
19..16
IPL12
15..12
IPL11
11..8
IPL10
7..4
IPL9
3..0
IPL8
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