參數(shù)資料
型號: RM7000
廠商: PMC-Sierra, Inc.
英文描述: RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released
中文描述: RM7000⑩微處理器與片上二級高速緩存數(shù)據(jù)發(fā)布
文件頁數(shù): 31/54頁
文件大?。?/td> 901K
代理商: RM7000
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
s Internal Use
Document ID: PMC-2002175, Issue 1
31
RM7000
Microprocessor with On-Chip Secondary Cache Datasheet
Released
Figure 10 Processor Block Write
Figure 11 Multiple Outstanding Reads
4.30 Data Prefetch
The RM7000 is the first PMC-Sierra design to support the MIPS IV integer data prefetch (
PREF
)
and floating-point data prefetch (
PREFX
) instructions. These instructions are used by the
compiler or by an assembly language programmer when it is known or suspected that an upcoming
data reference is going to miss in the cache. By appropriately placing a prefetch instruction, the
memory latency can be hidden under the execution of other instructions. If the execution of a
prefetch instruction would cause a memory management or address error exception the prefetch is
treated as a
NOP
.
SysClock
SysAD
Addr
Data0
Data1
Data2
Data3
SysCmd
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
Write
NData
NData
NData
NEOD
PRqst*
PAck*
Release*
TcMatch
SysClock
SysAD
SysCmd
ValidOut*
ValidIn*
Addr
1
Data1
Data1
Read
1
Data0
Addr
2
Data0
Data0
2
Read
2
NData
Master
Processor
Tertiary(Miss)
Tertiary(Miss)
Processor
Data1
2
NData
System
System
RspSwap*
1
2
3
4
5
6
7
8
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