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參數(shù)資料
| 型號： | RM7000 |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| 中文描述： | RM7000⑩微處理器與片上二級高速緩存數(shù)據(jù)發(fā)布 |
| 文件頁數(shù)： | 8/54頁 |
| 文件大小： | 901K |
| 代理商： | RM7000 |
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RM7000A
Microprocessor with On-Chip Secondary Cache Datasheet
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002175, Issue 1
8
Released
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10 Performance Counter Control .....................................................................................34
Table 11 Cause Register ...........................................................................................................36
Table 12 Interrupt Control Register ...........................................................................................36
Table 13 IPLLO Register ...........................................................................................................36
Table 14 IPLHI Register ............................................................................................................36
Table 15 Interrupt Vector Spacing .............................................................................................37
Table 16 Boot Time Mode Stream .............................................................................................38
Table 17 System interface Pins .................................................................................................39
Table 18 Clock/control interface Pins ........................................................................................40
Table 19 Tertiary cache interfacePins .......................................................................................41
Table 20 Interrupt Interface Pins ...............................................................................................42
Table 21 JTAG Interface Pins ....................................................................................................42
Table 22 Initialization Interface Pins ..........................................................................................42
Instruction Issue Rules ...............................................................................................12
Dual Issue Instruction Classes ...................................................................................13
ALU Operations .........................................................................................................15
Integer Multiply/Divide Operations ..............................................................................15
Floating Point Latencies and Repeat Rates ...............................................................17
Cache Attributes .........................................................................................................26
Cache Locking Control ...............................................................................................26
Penalty Cycles ............................................................................................................27
Watch Control Register ...............................................................................................33
相關PDF資料 |
PDF描述 |
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| RM7000-200S | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| RM7000-200T | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| RM7000-225S | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
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相關代理商/技術參數(shù) |
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| RM7000-250S | 制造商:QED 功能描述:Microprocessor, 64 Bit, 304 Pin, Plastic, BGA |
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