參數(shù)資料
型號: RM7000
廠商: PMC-Sierra, Inc.
英文描述: RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released
中文描述: RM7000⑩微處理器與片上二級高速緩存數(shù)據(jù)發(fā)布
文件頁數(shù): 40/54頁
文件大?。?/td> 901K
代理商: RM7000
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
s Internal Use
Document ID: PMC-2002175, Issue 1
40
RM7000
Microprocessor with On-Chip Secondary Cache Datasheet
Released
Table 18
Clock/control interface Pins
Pin Name
Type
SysClock
Input
SysADC(7:0)
Input/Output
System address/data check bus
An 8-bit bus containing parity check bits for the SysAD bus during data
cycles.
System command/data identifier bus
A 9-bit bus for command and data identifier transmission between the
processor and an external agent.
System Command/Data Identifier Bus Parity
For the RM7000, unused on input and zero on output.
SysCmd(8:0)
Input/Output
SysCmdP
Input/Output
Description
System clock
Master clock input used as the system interface reference clock. All
output timings are relative to this input clock. Pipeline operation
frequency is derived by multiplying this clock up by the factor selected
during boot initialization
Vcc for PLL
Quiet VccInt for the internal phase locked loop. Must be connected to
VccInt through a filter circuit.
Vss for PLL
Quiet Vss for the internal phase locked loop. Must be connected to
VssInt through a filter circuit.
VccP
Input
VssP
Input
Pin Name
Type
Description
相關(guān)PDF資料
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