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參數(shù)資料
| 型號： | RTC4573 |
| 廠商： | 愛普生（中國）有限公司 |
| 英文描述： | Serial RTC with Alarm and Timer |
| 中文描述： | 串行實時時鐘與鬧鐘和定時器 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 157K |
| 代理商： | RTC4573 |
1.2 Alarm registers (register 7 to register A)
Alarms can be set for days of the week, hours, and minutes. Bit 7 of each alarm register is an AE bit that can be
used to set an hourly alarm or a daily alarm. An alarm can also be set for multiple days of the week.However, when
using the day of the week alarm, also set either or both the hour and minute alarms. If the day of the week alarm is
set by itself, the alarm may not be output properly.When the AE bit is "0", the register in question and the timekeeping
register is compared; when the AE bit is "1", this indicates "don't care", and the registers are assumed to match,
regardless of the data.
1.3. Frequency output control register ( Reg-B )
FE bit is Frequency output enable bit. Source clock is selectable by FD4 and FD3 bits. And Count down rate is
selectable by FD0 , FD1 and FD2 bits. This frequency is output from FOUT terminal.
FOUT control ( Reg.B )
FD4 FD3
0
0
0
1
1
0
1
1
FD2
0
0
0
0
1
1
1
1
FD1
0
0
1
1
0
0
1
1
FD0
0
1
0
1
0
1
0
1
Div.
1 / 1
1 / 2
1 / 3
1 / 6
1 / 5
1 / 10
1 / 15
1 / 30
FOUT Duty
50%
50%
33%
50%
20%
50%
33%
50%
Source Clk.
32768Hz
1024Hz
32Hz
1Hz
1.4. Timer register( Reg-C to Reg-D )
Register-D is presetable binary down counter of 8 bits.
Source clock of this counter does setup by TD bit of Register-C.
Register-D does countdown by a period of selected source clock.
When data of register-D becomes 0, /TIRQ terminal changes to Low level.
In that time, register-D does written data reloads again if TI/TP bit is 1.
And counter does countdown repeatedly.
As a result, by a same period, interrupt occurs repeatedly.
When TIE bit of Register-E is "0", /TIRQ terminal keep high impedance.
When TI/TP bit is 0, Register-D does never reload the data.
Set TI/TP.TD,TIE and TE bits carefully, for perfect function of timer.
Source clock control for Timer ( Reg.C )
TD1
0
0
1
1
TD0
0
1
0 sec.
1 min.
Source Clk.
4096Hz
64Hz
update
update
Page-6
Aug.1998
When TEbit is 0, Register-D loads preset data, and keeps stop. Note:There isn't pause.
When TE bit is cleared, Register-D starts countdown from preset data.
Timer interrupt doesn't occur when set 0 in Register-D.
Therefore pay attention because 1 period error of source clock occurs as for timer time.
Timing of Timer start
DATA
TIRQ-PIN
TIMER COUNT DOWN
COUNT DOWN
CLK
DATA LOAD
ZERO
TD0
TD1
*
TE
Address C
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