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參數(shù)資料
| 型號(hào)： | RTC4573 |
| 廠商： | 愛普生（中國(guó)）有限公司 |
| 英文描述： | Serial RTC with Alarm and Timer |
| 中文描述： | 串行實(shí)時(shí)時(shí)鐘與鬧鐘和定時(shí)器 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 157K |
| 代理商： | RTC4573 |
Page-7
Aug.1998
1.5. Control register1 ( Reg-E )
Address
E
bit 7
*
bit 6
*
bit 5
*
bit 4
TI/TP
bit 3
AF
bit 2
TF
bit 1
AIE
bit 0
TIE
TI / TPbits
: ( Interrupt Signal Output Mode Select. Timer-Interrupt / Timer-Periodic )
output mode of timer signaling.
bit
0
1
TI / TP
TIRQ terminal is maintained by "L" till it is
written in "0" at TF bit when turn into interrupt
mode, and timer interrupt occurs, and, but,
timer interrupt signal does it with TIE=1
Timer interrupt signaling is set in a mode
repeatedly. When timer interrupt occurs,
TIRQ terminal is set at "L" immediately and,
but, does it with TIE=1. TF bit is set in "1",
and TIRQ terminal is set in Hi-Z after
approximately 3.9 m s, and TF bit holds "1" till
it is write clear by "0".
AF / TF bits
: ( Alarm Flag / Timer Flag )
When alarm occurs, AF bit is set in "1", and a timer is set in "1" at 0 oclock, and TF bit cant write in "1" at both bit.
AIE,TIE bits
: ( Alarm / Timer Interrupt Enable )
It is decided whether IRQ terminal drives it when alarm, timer interrupt occurred, and AIE corresponds in alarm, and
TIE corresponds to a timer, and AIRQ terminal is set in case of "0" AIE bit by Hi-Z, and TIRQ terminal is set in case of
"0" TIE bit by Hi-Z.
1.6 Control register 2 (register F )
Address
F
bit 7
*
bit 6
TEST
bit 5
STOP
bit 4
RESET
bit 3
HOLD
bit 2
*
bit 1
*
bit 0
*
·
TEST bit :
This is a test bit for Seiko-Epsons use.
Always set this bit to "0". When writing to the other bits in the CF register, be careful not to accidentally write a "1" to
this bit. This bit is cleared by setting CE low.
·
STOP bit
If this bit is set to "1", timekeeping stops (after 4KHz). If this bit is set back to "0", timekeeping resumes.
·
RESET bit
Setting this bit to "1" resets the counter below the seconds counter, stopping timekeeping. If a "1" is written to this bit,
it is cleared either by writing a "0" to this bit again with the auto increment function, or by setting CE low.
The only effect on timekeeping precision is a maximum error 61 [micro]s. This bit is unaffected by the status of other
bits.
·
HOLD bit
This bit stops carries to the ones digit of the seconds counter. Timekeeping continues below the seconds counter,
and if there was a carry to the seconds counter while HOLD = 1, compensation (by means of adding one second) is
made immediately (within 0 to 122 [micro]s) after HOLD is released.This bit is cleared by writing a "0" to it.
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