參數(shù)資料
型號(hào): RTL8100C-LF
廠(chǎng)商: Electronic Theatre Controls, Inc.
英文描述: SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
中文描述: 單芯片快速以太網(wǎng)控制器電源管理
文件頁(yè)數(shù): 36/73頁(yè)
文件大小: 652K
代理商: RTL8100C-LF
RTL8100C & RTL8100CL
Datasheet
Single-Chip Fast Ethernet Controller
28
Track ID: JATR-1076-21 Rev. 1.06
5.23. Multiple Interrupt Select Register
(Offset 005Ch-005Dh, R/W)
Note: The following is true when MulERINT=0 (bit17, RCR). When MulERINT=1, any received packet
invokes an early interrupt according to the MISR[11:0] setting in Early Mode.
If the received packet data is not a familiar protocol (IPX, IP, NDIS, etc.) to the RTL8100C(L),
RCR<ERTH[3:0]> will not be used to transfer data in early mode. This register will be written to the
received data length in order to make an early Rx interrupt for the unfamiliar protocol.
Table 23. Multiple Interrupt Select Register
Symbol
Description
-
Reserved.
MISR11-0
Multiple Interrupt Select Register.
Indicates that the RTL8100C(L) made an Rx interrupt after
transferring byte data into the system memory. If the value of these
bits is zero, there will be no early interrupt when the RTL8100C(L)
prepares to execute the first PCI transaction of the received data.
Bit1, 0 must be zero.
The ERTH3-0 bits should not be set to 0 when the multiple interrupt
select register is used.
Bit
15-12
11-0
R/W
-
R/W
5.24. PCI Revision ID (Offset 005Eh, R)
Table 24. PCI Revision ID
Description
Revision ID
The value in PCI Configuration Space offset 08h is 10h.
Bit
7-0
R/W
R
Symbol
5.25. Transmit Status of All Descriptors (TSAD) Register
(Offset 0060h-0061h, R/W)
Table 25. Transmit Status of All Descriptors (TSAD) Register
R/W
Symbol
Description
R
TOK3
TOK bit of Descriptor 3.
R
TOK2
TOK bit of Descriptor 2.
R
TOK1
TOK bit of Descriptor 1.
R
TOK0
TOK bit of Descriptor 0.
R
TUN3
TUN bit of Descriptor 3.
R
TUN2
TUN bit of Descriptor 2.
R
TUN1
TUN bit of Descriptor 1.
R
TUN0
TUN bit of Descriptor 0.
R
TABT3
TABT bit of Descriptor 3.
R
TABT2
TABT bit of Descriptor 2.
R
TABT1
TABT bit of Descriptor 1.
R
TABT0
TABT bit of Descriptor 0.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
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