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參數資料
| 型號： | RTL8100C-LF |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT |
| 中文描述： | 單芯片快速以太網控制器電源管理 |
| 文件頁數： | 41/73頁 |
| 文件大?。?/td> | 652K |
| 代理商： | RTL8100C-LF |
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RTL8100C & RTL8100CL
Datasheet
Single-Chip Fast Ethernet Controller
33
Track ID: JATR-1076-21 Rev. 1.06
5.33. NWay Test Register (Offset 0070h-0071h, R/W)
Table 33. NWay Test Register
Description/Usage
Reserved.
1: Set NWay to loopback mode
Reserved.
1: LED0 Pin indicates linkpulse
1: Auto negotiation experienced ability detect state
1: Auto negotiation experienced parallel detection fault state
1: Auto negotiation experienced link status check state
Bit
15-8
7
6-4
3
2
1
0
Name
-
NWLPBK
-
ENNWLE
FLAGABD
FLAGPDF
FLAGLSC
Default/Attribute
-
0, RW
-
0, RW
0, RO
0, RO
0, RO
5.34. RX_ER Counter (Offset 0072h-0073h, R)
Table 34. RX_ER Counter
Description/Usage
This 16-bit counter increments by 1 for each valid packet
received. It is cleared to zero by a read command.
Bit
15-0
Name
RXERCNT
Default/Attribute
h'[0000],
R
5.35. CS Configuration Register (Offset 0074h-0075h, R/W)
Table 35. CS Configuration Register
Description/Usage
1: Auto negotiation to speed up internal timer
Reserved.
Active low TPI link disable signal. When low, TPI still transmits
link pulses and TPI maintains a good link state.
The HEARTBEAT function is only valid in 10Mbps mode.
1: HEARTBEAT enable
0: HEARTBEAT disable
1: Enable jabber function
0: Disable jabber function
Used to login a forced good link at 100Mbps for diagnostic
purposes.
1: Disable
0: Enable
Assertion of this bit forces the disconnect function to be
bypassed.
Reserved.
This bit indicates the status of the connection.
1: Valid connected link detected
0: Disconnected link detected
Assertion of this bit configures the LED1 pin to indicate
connection status.
Reserved.
Bypass Scramble.
Bit
15
14-10
9
Name
Testfun
-
LD
Default/Attribute
0, WO
-
1, RW
8
HEARTBEAT
1, RW
7
JBEN
1, RW
6
F_LINK_100
1, RW
5
F_Connect
0, RW
4
3
-
-
Con_status
0, RO
2
Con_status_En
0, RW
1
0
-
-
PASS_SCR
0, RW
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