參數(shù)資料
型號： RTL8100L
廠商： Electronic Theatre Controls, Inc.
英文描述： REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
中文描述： 瑞昱單芯片快速以太網(wǎng)控制器電源管理
文件頁數(shù)： 31/58頁
文件大小： 657K
代理商： RTL8100L
RTL8100B(L)
2001-11-9
Rev.1.41
31
5.28 Config5: Configuration Register 5
(Offset 00D8h, R/W)
This register, unlike other Config registers, is not protected by 93C46 Command register. I.e. there is no need to enable Config
register write prior to writing to Config5.
Bit
7
6
R/W
-
R/W
Symbol
-
BWF
Description
Reserved
Broadcast Wakeup Frame:
1: Enable Broadcast Wakeup Frame with mask bytes of only DID
field = FF FF FF FF FF FF.
0: Default value. Disable Broadcast Wakeup Frame with mask bytes
of only DID field = FF FF FF FF FF FF.
The power-on default value of this bit is 0.
Multicast Wakeup Frame:
1: Enable Multicast Wakeup Frame with mask bytes of only DID
field, which is a multicast address.
0: Default value. Disable Multicast Wakeup Frame with mask bytes
of only DID field, which is a multicast address.
The power-on default value of this bit is 0.
Unicast Wakeup Frame:
1: Enable Unicast Wakeup Frame with mask bytes of only DID field,
which is its own physical address.
0: Default value. Disable Unicast Wakeup Frame with mask bytes of
only DID field, which is its own physical address.
The power-on default value of this bit is 0.
FIFO Address Pointer:
(Realtek internal use only to test FIFO SRAM)
1: Both Rx and Tx FIFO address pointers are updated in descending
way from 1FFh and downwards. The initial FIFO address pointer is
1FFh.
0: (Power-on) default value. Both Rx and Tx FIFO address pointers
are updated in ascending way from 0 and upwards. The initial FIFO
address pointer is 0.
Note: This bit does not participate in EEPROM auto-load. The FIFO
address pointers can not be reset, except initial power-on.
The power-on default value of this bit is 0.
Link Down Power Saving mode:
1: Disable.
0: Enable. When cable is disconnected(Link Down), the analog part
will power down itself (PHY Tx part & part of twister) automatically
except PHY Rx part and part of twister to monitor SD signal in case
that cable is re-connected and Link should be established again.
LANWake signal enable/disable:
1: Enable LANWake signal.
0: Disable LANWake signal.
PME_Status bit:
Always sticky/can be reset by PCI RST# and software.
1: The PME_Status bit can be reset by PCI reset or by software.
0: The PME_Status bit can only be reset by software.
5
R/W
MWF
4
R/W
UWF
3
R/W
FIFOAddrPtr
2
R/W
LDPS
1
R/W
LANWake
0
R/W
PME_STS
Config5 register, offset D8h: (SYM_ERR register is changed to Config5, the function of SYM_ERR register is no longer
supported by RTL8100B(L).)
The 3 bits (bit2-0) are auto-loaded from EEPROM Config5 byte to RTL8100B(L) Config5 register.
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