![](http://datasheet.mmic.net.cn/330000/RTL8139C_datasheet_16451889/RTL8139C_43.png)
RTL8139C(L)
2002/01/10
Rev.1.4
43
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
|
3Bh
3Ch
3Dh
3Eh
3Fh
40h
|
FFh
R
R
R
R
R
R
R
W
R
W
R/W
R/W
R
0
0
1
0
0
1
0
-
0
0
0
1
0
0
0
0
-
0
0
0
1
0
1
0
0
-
0
0
0
0
1
0
0
0
-
0
0
0
1
0
1
0
0
-
0
0
0
1
0
0
0
0
-
0
-
0
0
0
0
0
0
0
0
0
-
0
-
0
0
0
0
0
1
1
1
0
SVID
SMID
BMAR
Cap-Ptr
-
BROMEN
0
-
0
0
Ptr0
BMAR15 BMAR14 BMAR13 BMAR12 BMAR11
0
0
0
0
0
0
Ptr7
Ptr6
Ptr5
0
0
0
0
Ptr4
Ptr3
Ptr2
Ptr1
RESERVED(ALL 0)
ILR
IPR
R/W
R
R
R
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
MNGNT
MXLAT
-
RESERVED(ALL 0)
8.4 PCI Power Management Functions
The RTL8139C(L) is compliant to ACPI (Rev 1.0, 1.0b, 2.0), PCI Power Management (Rev 1.1), and Network Device Class
Power Management Reference Specification (V1.0, 1.0a, 2.0), such as to support OS Directed Power Management (OSPM)
environment. To support this, the RTL8139C(L) provides the following capabilities:
The RTL8139C(L) can monitor the network for a Wakeup Frame, a Magic Packet, or a Link Change, and notify the
system via PME# when such a packet or event arrives. Then, the whole system can be restored to a working state to
process the incoming jobs.
The RTL8139C(L) can be isolated from the PCI bus automatically with the auxiliary power circuit when the PCI bus is
in B3 state, i.e. when the power on the PCI bus is removed. When the motherboard includes a built-in RTL8139C(L)
single-chip fast Ethernet controller, the RTL8139C(L) can be disabled when needed by pulling the isolate pin low to 0V.
When the RTL8139C(L) is in power down mode (D1 ~ D3):
The Rx state machine is stopped, and the RTL8139C(L) keeps monitoring the network for wakeup events such as Magic
Packet, Wakeup Frame, and/or Link Change, in order to wake up the system. When in power down mode, the
RTL8139C(L) will not reflect the status of any incoming packets in the ISR register and will not receive any packets into
the Rx FIFO.
The FIFO status and the packets which are already contained in the Rx FIFO before entering power down mode are kept
by the RTL8139C(L) during power down mode.
The transmission is stopped. The action of PCI bus master mode is stopped, as well. The Tx FIFO is kept.
After restoration to a D0 state, the PCI bus master mode continues to transfer the data, which is not yet moved into the Tx
FIFO from the last break. The packet that was not transmitted completely last time is transmitted again.
D3cold_support_PME bit(bit15, PMC register) & Aux_I_b2:0 (bit8:6, PMC register) in PCI configuration space.
If 9346 D3cold_support_PME bit(bit15, PMC) = 1, the above 4 bits depend on the existence of Aux. power.
If 9346 D3cold_support_PME bit(bit15, PMC) = 0, the above 4 bits are all 0's.
Examples:
1.
If 9346 D3c_support_PME = 1,
If Aux. power exists, then PMC in PCI config space is the same as 9346 PMC, i.e. if 9346 PMC = C2 F7,