![](http://datasheet.mmic.net.cn/330000/RTL8139C_datasheet_16451889/RTL8139C_45.png)
RTL8139C(L)
2002/01/10
Rev.1.4
45
**
last masked byte:
The last byte of the masked bytes of the received Wakeup Frame packet within offset 12 to 75 (in 8-bit CRC mode) should
match the last byte of the masked bytes of the sample Wakeup Frame provided by the local machine’s OS.
The PME# signal is asserted only when the following conditions are met:
The PMEn bit (bit0, CONFIG1) is set to 1.
The PME_En bit (bit8, PMCSR) in PCI Configuration Space is set to 1.
The RTL8139C(L) may assert PME# in current power state, or the RTL8139C(L) is in isolation state. Refer to
PME_Support(bit15-11) of the PMC register in PCI Configuration Space.
Magic Packet, LinkUp, or Wakeup Frame has occurred.
Note: Writing a 1 to the PME_Status (bit15) of the PMCSR register in the PCI Configuration Space will clear this bit
and cause the RTL8139C(L) to stop asserting a PME# (if enabled).
When the RTL8139C(L) is in power down mode, ex. D1-D3, the IO, MEM, and Boot ROM space are all disabled. After RST#
is asserted, the power state must be changed to D0 if the original power state is D3
cold
. There is no hardware enforced delays at
RTL8139C(L)’s power state. When in ACPI mode, the RTL8139C(L) does not support PME from D0, due to the setting of the
PMC register. This setting comes from EEPROM.
The RTL8139C(L) also supports the LAN WAKE-UP function. The LWAKE pin is used to notify the motherboard to execute
the wake-up process whenever the RTL8139C(L) receives a wakeup event, such as Magic Packet.
The LWAKE signal is asserted according the following setting.
LWPME bit (bit4, CONFIG4):
0: The LWAKE is asserted whenever there is wakeup event occurs.
1: The LWAKE can only be asserted when the PMEB is asserted and the ISOLATEB is low.
Bit1 of DELAY byte(offset 1Fh, EEPROM):
0: LWAKE signal is disabled.
1: LWAKE signal is enabled
8.5 Vital Product Data (VPD)
Bit 31 of the VPD is used to issue the VPD read/write command and is also a flag used to indicate if the transfer of data between
the VPD data register and the 93C46/93C56 has been completed or not.
1.
Write VPD register: (write data to 93C46/93C56)Write the flag bit to a one at the same time the VPD address is written.
When the flag bit is set to zero by the RTL8139C(L), the VPD data (all 4 bytes) has been transferred from the VPD data
register to 93C46/93C56.
2.
Read VPD register: (read data from 93C46/93C56) Write the flag bit to a zero at the same time the VPD address is written.
When the flag bit is set to one by the RTL8139C(L), the VPD data (all 4 bytes) has been transferred from the 93C46/93C56
to the VPD data register.