參數(shù)資料
型號: RTL8305S
廠商: Electronic Theatre Controls, Inc.
英文描述: 5-PORT 10/100 MBPS SINGLE CHIP SWITCH CONTROLLER
中文描述: 5端口10/100 Mbps單片開關(guān)控制器
文件頁數(shù): 12/24頁
文件大?。?/td> 417K
代理商: RTL8305S
RTL8305S
2002/02/19
Rev. 1.2
12
6.3.5 100Base-TX Transmit Function
The 100Base-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ/NRZI conversion,
and MLT3 encoding. After 4B/5B coding, the 5-bit serial data stream is scrambled as defined by the TP-PMD Stream Cipher
function to flatten the power spectrum energy such that EMI effects can be significantly reduced.
The scrambled seed is unique for each port, based on PHY addresses. After scrambling, the bit stream is driven into the
network medium in the form of MLT-3 signaling. Multi-level signaling technology moves the power spectrum energy from
high frequency to low frequency, which also benefits EMI emission issues.
6.3.6 100Base-TX Receive Function
The receive path includes a receiver composed of an adaptive equalizer and DC restoration circuits, to compensate for the
incoming distortion of the MLT-3 signal, MLT-3 to NRZI, NRZI to NRZ converter to convert analog signaling to a digital
bit-stream, and a PLL circuit to clock data bits precisely with minimum bit error rate. The de-scrambler, 5B/4B decoder and
serial-to-parallel conversion circuits follow. Finally, the converted parallel data is fed into the MAC.
6.3.7 Power Saving Mode
The RTL8305S implements power saving mode on per port basis. A port automatically enters power saving mode 10 seconds
after the cable is disconnected from it. Once a port enters power saving mode, it transmits normal link pulses only on its
TXOP/TXON pins and keeps monitoring RXIP/RXIN to try to detect any incoming signals, which might be a 100Base-TX
MLT-3 idle pattern, 10Base-T link pulses or Nway’s FLP (Fast Link Pulses). After it detects any incoming signals, it wakes up
from the power saving mode and operates in the normal mode according to the result of the connection.
6.4 LED
The RTL8305S supports three parallel LEDs for each port. LED_ACT indicates activity and link status, LED_DPX indicates
collision and duplex status, and LED_SPD indicates operating speed with state ‘0’ equal to 100Mbps. All LED pins are active
low, and blink when presenting activity and collision states. During power-on reset, the RTL8305S supports diagnostics of
chip reset and LED functions by blinking all parallel LEDs once. This function can be disabled by asserting
DIS_RST_BLINK# to 0. LED_BLINK_TIME determines LED blinking period for activity and collision, with 1 = 43ms and 0
= 120ms. LEDs corresponding to port 4 can be tri-stated (disable LED functions) for MII port applications by pulling
ENP4LED low.
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