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參數資料
| 型號： | RTL8305S |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 5-PORT 10/100 MBPS SINGLE CHIP SWITCH CONTROLLER |
| 中文描述： | 5端口10/100 Mbps單片開關控制器 |
| 文件頁數： | 8/24頁 |
| 文件大?。?/td> | 417K |
| 代理商： | RTL8305S |
RTL8305S
2002/02/19
Rev. 1.2
8
5.4 LED Pins
Pin Name
LED_ACT[4:0]
Pin No.
119,116
111,108
104
118,115
110,107
103
120,117
113,109
105
Type
O
Description
Default
1
Active low (Link + Activity) LED pins.
LED_DPX[4:0]
O
Active low (Fullduplex + Collision) LED pins.
1
LED_SPD[4:0]
O
Active low Speed100 LED pins.
1
5.5 Power Pins
Pin Name
TVDD
Pin No.
5,6,21
22,37
13,14,29
30,126
125
38
43,53,62
70,87,100
106,114
1,10,17
26,33
2,9,18
25,34
123
64
39,50,65
79,94,102
112,122
Type
P
Description
Default
3.3V Analog Transmit Power
RVDD
P
3.3V Analog Receive Power
AVDD
MVDD
VDD
P
P
P
3.3V Analog Power
3.3V Internal RAM Power
3.3V Digital Power
RGND
P
Analog Ground
TGND
P
Analog Ground
AGND
MGND
GND
P
P
P
Analog GND
Internal RAM GND
Digital GND
5.6 Miscellaneous Pins
Pin Name
Pin No.
44
45
71
40
Type
I
O
O
I
Description
Default
X1
X2
CK25MOUT
RESET#
25MHz crystal or oscillator clock input
To crystal input. When using an oscillator this pin should be kept floating.
25MHz clock output
Active low reset signal. To complete the reset function, this pin must be
asserted for at least 10ms. After reset, about 30ms is needed for the
RTL8305S to complete the internal test function and initialization.
Control transmit output waveform Vpp. This pin should be grounded
through a 1.96K
resistor.
Test clock
I/O Test data
IBREF
124
A
TESTCLK
TESTDATA
5.7 Reserved Pins
41
42
I
Pin Name
RESERVED
Pin No.
69
Type
I
Description
Default
1
This pin is reserved for internal use and should be left floating.
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