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參數(shù)資料
| 型號： | RTL8308B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | REALTEK SINGLE CHIP 8-PORT 10/100 ETHERNET SWITCH CONTROLLER WITH EMBEDDED MEMORY |
| 中文描述： | 瑞昱單片8端口10/100以太網(wǎng)交換機(jī)控制器，嵌入式存儲(chǔ)器 |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 397K |
| 代理商： | RTL8308B |
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RTL8308B
2002/01/23
Rev. 2.0
10
6.2.2 Auto Negotiation
Each individual port can operate at 10Mbps or 100Mbps in half or full duplex mode, and can indicate support of
IEEE 802.3x flow control. The operating modes for each port can be negotiated between the MAC and PHY
devices after power up if auto-negotiation is enabled for that port. Auto-negotiation may be enabled for each port
by setting the corresponding auto-negotiation parameter through a configuration pin, EEPROM or serial
configuration interface. This provides for unmanaged operation, when using PHY devices that support this
signaling scheme.
6.2.3 MII Interface
Through the MII interface, the 10/100Mbps ports support a number of options, such as full/half duplex and
10M/100M bit rate. The architecture for the 100Mbps interface is similar to that for 10Mbps. This permits the
interface to support both 10 and 100Mbps operation. When operated at 10Mbps, the ports support nibble mode at
2.5 MHz clock rate.
6.2.4 RMII interface
The RTL8308B provides a 10/100 Mbps low pin count RMII interface for use between PHY and RTL8308. The
MAC of each port of RTL8308B is connected to the PHY through the standard RMII interface. The RMII is
capable of supporting 10Mbps and 100Mbps data rates. A single clock reference, 50MHz, sourced from an external
clock input is used for receiving and transmitting.
It also provides independent 2 bit wide (di-bit) transmit and receive data paths. As the REFCLK is 10 times the
data rate in 10Mbps mode, each data di-bit must be output on TXD[1:0] and input on RXD[1:0] for ten consecutive
REFCLK cycles. The RTL8308B can regenerate the COL signal of the MII internally by ANDing TXEN and CRS
as recovered from CRSDV. Note that TXEN cannot be ANDed directly with CRSDV since CRSDV may toggle at
the end of the frame to provide separation of RXDV and CRS.
Prior to any data transaction, RTL8308B will output di-bits of ‘01’ as preamble signal. After the preamble, a ‘11’
signal is used to indicate the start of the frame. For reception, the received data (RXD) is sampled by the rising
edge of the REFCLK. Assertion of the CRSDV signal indicates that the receive channel is active. The di-bit
RXD[1:0] is nominally ‘00’ until the PHY detects a valid SFD and sends a ‘01’ preamble. Valid data will follow
SFD. For transmission, TXEN is asserted when the first preamble nibble is sent on the transmit data (TXD) lines.
The transmit data is clocked out by the rising edge of the reference clock.
RMII Specification Signals are listed below:
Signal Name
Direction
(with respect
to the PHY)
to the RTL8308)
REFCLK
Input
Input
Direction
(with respect
Use
Synchronous clock reference for receive,
transmit and control interface.
Carrier Sense/Receive Data Valid
Receive Date
Transmit Enable
Transmit Data
CRSDV
RXD[1:0]
TXEN
TXD[1:0]
Output
Output
Input
Input
Input
Input
Output
Output
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| RU4D | SDR Cable Assembly; Connector Type A:micro D Ribbon Plug; Connector Type B:micro D Ribbon Plug; Cable Length:2m; No. of Contacts:26; Pitch Spacing:0.8mm RoHS Compliant: Yes |
| RU4D | Damper Diodes (For Display) |
相關(guān)代理商/技術(shù)參數(shù) |
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| RTL8309SB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE-CHIP 9-PORT 10/100MBPS SWITCH CONTROLLER |
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| RTL8316 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Specifications |
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