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參數(shù)資料
| 型號： | RTL8308B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | REALTEK SINGLE CHIP 8-PORT 10/100 ETHERNET SWITCH CONTROLLER WITH EMBEDDED MEMORY |
| 中文描述： | 瑞昱單片8端口10/100以太網(wǎng)交換機(jī)控制器，嵌入式存儲器 |
| 文件頁數(shù)： | 9/28頁 |
| 文件大小： | 397K |
| 代理商： | RTL8308B |
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RTL8308B
2002/01/23
Rev. 2.0
9
6. Functional Description
6.1 Reset
The minimum required reset duration is 1us. After power on reset, the RTL8308B will determine some features
from the ENFCTRL, ENBKPRS and ENBrdCtrl pins, auto-load the content of 24LC02 serial EEPROM, and write
abilities to connected PHY management registers via MDC/MDIO. It is recommended that the RTL8308B and
connected PHYs use the same reset signal source. The PHY reset must be completed before the RTL8308B.
6.2 Network Interface
The RTL8308B has 8 10/100 Mbps Ethernet ports (port 0 to port 7) with Reduced MII (R-MII) interfaces. It has 1
MII port in addition to the 4 R-MII ports for 10/100Mbps Ethernet transceivers. Note that an MII interface operates
at 25MHz in 100Mbps transmission and 2.5MHz for 10Mbps transmission. Reduced MII interfaces use the same
50MHz clock rate for both 10Mbps and 100Mbps operation. All MII interfaces support auto-negotiation for
transmission speeds, duplex modes and flow control options.
6.2.1 Medium Access Control
The RTL8308B implements the IEEE Std 802.3 binary exponential back-off algorithm and conforms to IEEE
802.3 specifications.
Data received from the PHY is interpreted and assembled into the external buffer memory by the RTL8308B flow
controller. Interpretation involves detection and removal of the preamble, extraction of the address and FCS
verification. Also included is a jabber-detection timer to detect frames of greater than maximum length being
received on the network. In 10Mbps mode, the raw data received from the PHY as input is converted to 8-bit width
before further processing. Similarly, in 100Mbps mode, the data received from the external PHY is converted to
8-bit data width in the shifter. The data is then synchronized to the internal clock of the RTL8308B. Once the
100Mbps data has been deserialized it is handled no differently than the 10Mbps data. By default, the RTL8308B
detects collision signals by itself, which makes normal and reverse MII connection easy. Because signals from the
PHY are not synchronized with internal clocks of the RTL8308B, the Rx FIFO adjusts timing differences between
external & internal clocks. Data transmission requires more processing and data handling than data reception. This
is due to the overhead of implementing collision detection and recovery logic. Data entering from the FIFO is
serialized for transmission at the transmit clock rate (this also requires the data to be synchronized to the transmit
clock rate from the internal clock). Because the transmit clock is asynchronous with the internal clock of the
RTL8308B, the Tx FIFO is needed for timing adjustment. The Tx FIFO will also transmit JAM pattern and
PAUSE frames to work with the flow control mechanism in the Flow Control Unit.
The Tx FIFO handles the output of data to the PHY devices, and several error states are handled. If a collision is
detected in half duplex mode, the state machine jams the output. If the collision was late (after the first 64-bytes
have been transmitted), the frame is lost. If it is an early collision, the controller backs off before retrying. While
operating in full duplex mode, both carrier-sense (CRS) mode and collision-sensing modes are disabled. Internally,
frame data only is removed from buffer memory once it has been successfully transmitted without collision (for the
half-duplex ports). Transmission recovery also is handled in this state machine. If a collision is detected, frame
recovery and retransmission are initiated.
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