參數(shù)資料
型號: S12VREGV1D
廠商: Motorola, Inc.
英文描述: MC9S12DT128 Device User Guide V02.09
中文描述: MC9S12DT128設備的用戶手冊V02.09
文件頁數(shù): 119/138頁
文件大?。?/td> 2083K
代理商: S12VREGV1D
MC9S12DT128 Device User Guide — V02.09
119
A.5.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLL′s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.
A.5.3.1 XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
Figure A-2 Basic PLL functional diagram
The following procedure can be used to calculate the resistance and capacitance values using typical
values for K
1
, f
1
and i
ch
from
Table A-16
.
The grey boxes show the calculation for f
VCO
= 50MHz and f
ref
= 1MHz. E.g., these frequencies are used
for f
OSC
= 4MHz and a 25MHz bus clock.
The VCO Gain at the desired VCO frequency is approximated by:
f
f
(
)
K
1
1V
=
100
=
The phase detector relationship is given by:
i
ch
is the current in tracking mode.
f
osc
1
refdv+1
f
ref
Phase
Detector
VCO
K
V
1
synr+1
f
vco
Loop Divider
K
Φ
1
2
f
cmp
C
s
R
C
p
VDDPLL
XFC Pin
K
V
K
1
e
-----------------------
e
60
50
(
-----------------------
)
100
= -90.48MHz/V
K
Φ
i
ch
K
V
=
=
316.7Hz/
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