參數(shù)資料
型號: S29AL004D70DGE014
廠商: SPANSION LLC
元件分類: PROM
英文描述: 256K X 16 FLASH 3V PROM, 70 ns, UUC44
封裝: 3.90 X 2.33 MM, DIE
文件頁數(shù): 6/13頁
文件大?。?/td> 244K
代理商: S29AL004D70DGE014
2
S29AL004D Known Good Die
S29AL004D_KGD_A2 April 14, 2006
Data
Shee t
Suppleme nt
General Description
The S29AL004D in Known Good Die (KGD) form is an 4 Mbit, 3.0 volt-only Flash
memory. Spansion defines KGD as standard product in die form, tested for func-
tionality and speed. Spansion KGD products have the same reliability and quality
as Spansion products in packaged form.
S29AL004D Features
The S29AL004D is an 4 Mbit, 3.0 volt-only Flash memory organized as 524,288
bytes or 262,144 words. The word-wide data (x16) appears on DQ15–DQ0; the
byte-wide (x8) data appears on DQ7–DQ0. To eliminate bus contention, the de-
vice has separate chip enable (CE#), write enable (WE#) and output enable
(OE#) controls.
The device requires only a single 3.0 volt power supply for both read and write
functions. Internally generated and regulated voltages are provided for the pro-
gram and erase operations. No VPP is required for program or erase operations.
The device can also be programmed in standard EPROM programmers.
The device is entirely command set compatible with the JEDEC single-power-
supply Flash standard. Commands are written to the command register using
standard microprocessor write timings. Register contents serve as input to an in-
ternal state-machine that controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This
initiates the Embedded Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies proper cell margin. The
Unlock Bypass mode facilitates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates
the Embedded Erase algorithm—an internal algorithm that automatically pre-
programs the array (if it is not already programmed) before executing the erase
operation. During erase, the device automatically times the erase pulse widths
and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by
observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (tog-
gle) status bits. After a program or erase cycle is completed, the device is ready
to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low VCC detector that automat-
ically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase operations in any combina-
tion of the sectors of memory. This can be achieved in-system or via
programming equipment.
The Erase Suspend feature enables the user to put erase on hold for any period
of time to read data from, or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
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