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| 型號(hào)： | S29CL032J0RFAN130 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 1M X 32 FLASH 3.3V PROM, 48 ns, PBGA80 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-80 |
| 文件頁(yè)數(shù)： | 61/78頁(yè) |
| 文件大?。?/td> | 1825K |
| 代理商： | S29CL032J0RFAN130 |
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62
S29CD-J & S29CL-J Flash Family
S29CD-J_CL-J_00_B1 September27,2006
Prel imi n ary
18.6 Erase/Program Operations
Notes:
1. Not 100% tested.
2. See Command Definitions on page 71 for more information.
3. Program Erase Parameters are the same, regardless of Synchronous or Asynchronous mode.
Note: PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 18.8 Program Operation Timings
Table 18.5 Erase/Program Operations
Parameter
Description
All Speed Options
JEDEC
Std.
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
60
ns
tAVWL
tAS
Address Setup Time
Min
0
ns
tWLAX
tAH
Address Hold Time
Min
25
ns
tDVWH
tDS
Data Setup to WE# Rising Edge
Min
18
ns
tWHDX
tDH
Data Hold from WE# Rising Edge
Min
2
ns
tGHWL
Read Recovery Time Before Write
(OE# High to WE# Low) (Note 1)
Min
0
ns
tELWL
tCS
CE# Setup Time
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
tWP
WE# Width
Min
25
ns
tWHWL
tWPH
Write Pulse Width High
Min
30
ns
Double-Word
Typ
9
s
Typ
0.5
sec.
tVCS
Min
50
s
tRB
Recovery Time from RY/BY# (Note 1)
Min
0
ns
Max
90
ns
tWPWS
WP# Setup to WE# Rising Edge with Command
Min
20
ns
Max
2
ns
OE#
WE#
CE#
VCC
Data
Addresses
tDS
tAH
tDH
tWP
PD
tWHWH1
tWC
tAS
tWPH
tVCS
555h
PA
Read Status Data (last two cycles)
A0h
tCS
Statu
DOUT
Program Command Sequence (last two cycles)
RY/BY#
tRB
tBUSY
tCH
PA
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