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參數(shù)資料
| 型號： | S5D0127X01 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | MULTISTANDARD VIDEO DECODER/SCALER |
| 中文描述： | 多標準視頻解碼器/倍線器 |
| 文件頁數(shù)： | 11/96頁 |
| 文件大?。?/td> | 1509K |
| 代理商： | S5D0127X01 |
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ELECTRONICS
S5D0127X01 Data Sheet
MULTIMEDIA VIDEO
PAGE 11 OF 96
Modified on May/04/2000
When in digital input mode, all programmable timing registers (such as HAVB,HAVE, HS2B etc.) are still functional.
If HS1 and VS are programmed as inputs, the associated output timing controls such as HS1B,E will have no
effect. An example of horizontal timing for digital input is shown in Figure 4.
Figure 4. Horizontal Timing for EXV Port as Digital Input
1.1.5. Additional Information for Analog Component Video Input
For the S5D0127X01 to correctly set the V component phase in analog component video input mode, PID (pin 17)
and PORTA (pin 58) need to be connected together. PORTA has to be configured as input (
DIRA
= 0) and
connected to the internal CBG signal (
DATAA
[2:0] = 3).
It is also recommended that external clamp circuit be used for Cb and Cr inputs (before the coupling caps) and the
internal chroma clamp be disabled (
COFFENB
= 1) due to slight Cb/Cr leakage.
80 10 80 10 80 10 U
0
Y
0
V
0
Y
1
U
2
Y
2
V
2
Y
3
U
4
Y
4
V
4
Y
5
U
6
Y
6
V
6
Y
7
U
x
Y
x
V
x
Y
x
U
x
HAV
CK
CK2
HS1
80 10 80 10 80 10 U
0
Y
0
V
0
Y
1
U
2
Y
2
V
2
Y
3
U
4
Y
4
V
4
Y
5
U
6
Y
6
V
6
Y
7
U
x
Y
x
V
x
Y
x
U
x
Y
x
V
x
Y
x
V
x
Programmable, when an
output - Any input phase
is acceptable
Fully programmable HAVB location
based on internal counter
HAV -- fully programmable,
Defines location of first, last pixel
and defines Cb,Y,Cr data location
Data group delay through chip --
EXV[7:0]
Constant to internal counter reference
Fully programmable
HAVE location
The CK2 output clock phasing
is aligned to the HAV leading
edge
CK can be input or output
This HS1 location can also come
From a 656 SAV code
Y[7:0]
Y output for OFMT=2 is
shown, any 8 or 16 bit
output format is allowed.
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