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ELECTRONICS
S5D0127X01 Data Sheet
MULTIMEDIA VIDEO
PAGE 46 OF 96
Modified on May/04/2000
1.10.3. 656 Op Code Vertical Transitions
The vertical transition locations of the various 656 Op Codes are shown in Figure 36 and Figure 37. Note that for
proper transition locations of the SAV and EAV Op Codes
VSE
=0 and
VALIGN
=1.
1.11. HOST INTERFACE
The S5D0127X01 supports the IIC serial interface for programming the chip registers.
1.11.1. IIC Interface
The two wire interface consists of the SCLK and SDAT signals. Data can be written to or read from the
S5D0127X01. For both read and write, each byte is transferred MSB first, and the data bit is valid when the SCLK
is high.
To write to the slave device, the host initiates a transfer cycle with a START signal. The START signal is HIGH to
LOW transition on the SDAT while the SCLK is high. The host then sends a byte consisting of the 7-bit slave device
ID and a 0 in the R/W bit. The arrangement for the slave device ID and the R/W bit is depicted in Figure 38. AEX1
and AEX0 are configuration pins used to configure the S5D0127X01 to use one of the four addresses. Up to four
S5D0127X01’s can be used in one system each with a unique address.
Figure 38. IIC Slave Device ID and R/W Byte
Table 13: 656 and TASKB 656 Op Codes
Condition
SAV / EAV Output Sequence --
Reference Output timing pic-
tures
656 FVH values
Field
Vertical
Horizontal
A
B
C
D
D’
F
V
H
Field 2
Vertical Blank
End Active Video
FFh
00h
00h
F1h
7Fh
1
1
1
Field 2
Vertical Blank
Start Active Video
FFh
00h
00h
ECh
62h
1
1
0
Field 2
Vertical Active
End Active Video
FFh
00h
00h
DAh
54h
1
0
1
Field 2
Vertical Active
Start Active Video
FFh
00h
00h
C7h
49h
1
0
0
Field 1
Vertical Blank
End Active Video
FFh
00h
00h
B6h
38h
0
1
1
Field 1
Vertical Blank
Start Active Video
FFh
00h
00h
ABh
24h
0
1
0
Field 1
Vertical Active
End Active Video
FFh
00h
00h
9Dh
13h
0
0
1
Field 1
Vertical Active
Start Active Video
FFh
00h
00h
80h
0Eh
0
0
0
1
1
0
1
1
AEX1
AEX0
R/W
msb
lsb
slave device ID