參數(shù)資料
型號: S5D0127X01
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: MULTISTANDARD VIDEO DECODER/SCALER
中文描述: 多標準視頻解碼器/倍線器
文件頁數(shù): 14/96頁
文件大?。?/td> 1509K
代理商: S5D0127X01
ELECTRONICS
S5D0127X01 Data Sheet
MULTIMEDIA VIDEO
PAGE 14 OF 96
Modified on May/04/2000
An additional signal, HAV, is provided for horizontal video cropping. This signal has programmable polarity, start
and stop locations. Two 11-bit registers,
HAVB
and
HAVE
, are used to define the first and last pixel locations of the
horizontal portion of the cropped video. Numbers programmed into these registers are used as offset to the default
locations as shown in Table 4. Note that even though
HAVB
and
HAVE
have 1-CK resolution, the difference
between them should be maintained at multiple of 4 CKs for correct output.
Table 4 shows the default edge locations relative to the midway of the falling edge of the analog horizontal sync.
Note the numbers shown are in multiple of CK clocks. Figure 6 shows the approximate locations for the horizontal
timing signals. Horizontal timing signals used for scaling will be described in Section 1.6.1.
Table 4: Horizontal Timing Signal Edge Locations (in # of CK)
Description
Signal
60 Hz
50 Hz
CCIR 601
(modulo 1716)
Square Pixel
(modulo 1560)
CCIR 601
(modulo 1728)
Square Pixel
(modulo 1888)
Chip delay
120
120
120
120
Sync gate (1-CK pulse)
SYG
72
72
72
72
Back porch gate
BPG
[147 222]
[129 204]
[154 234]
[168 254]
Color burst gate (1-CK pulse)
CBG
222
204
234
254
Wide color burst gate
CBGW
[159 254]
[147 233]
[173 254]
[186 277]
Two pulses per line (1-CK each
pulse)
FH2
42, 900
42, 822
42, 906
42, 986
Default one pulse per line
HS1
[65 238]
[45 220]
[69 250]
[65 270]
Default one pulse per line
HS2
[65 238]
[45 220]
[69 250]
[65 270]
Default horizontal cropping
HAV
[351 75]
[334 58]
[379 91]
[415 59]
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